Construction of memory circuits using unreliable components based on low-density parity-check codes

Miloš Ivković, Shashi Kiran Chilappagari, Bane V Vasic

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

In this paper, we analyze storage circuits constructed from unreliable memory components. We propose a memory construction, using low-density parity-check codes, based on a construction originally made by Taylor. The storage circuit consists of unreliable memory cells along with a correcting circuit. The correcting circuit is also constructed from unreliable logic gates along with a small number of perfect gates. The modified construction enables the memory device to perform better than the original construction. We present numerical results supporting our claims.

Original languageEnglish (US)
Title of host publicationGLOBECOM - IEEE Global Telecommunications Conference
DOIs
StatePublished - 2006
EventIEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference - San Francisco, CA, United States
Duration: Nov 27 2006Dec 1 2006

Other

OtherIEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference
CountryUnited States
CitySan Francisco, CA
Period11/27/0612/1/06

Fingerprint

Data storage equipment
Networks (circuits)
Logic gates

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Ivković, M., Chilappagari, S. K., & Vasic, B. V. (2006). Construction of memory circuits using unreliable components based on low-density parity-check codes. In GLOBECOM - IEEE Global Telecommunications Conference [4150789] https://doi.org/10.1109/GLOCOM.2006.159

Construction of memory circuits using unreliable components based on low-density parity-check codes. / Ivković, Miloš; Chilappagari, Shashi Kiran; Vasic, Bane V.

GLOBECOM - IEEE Global Telecommunications Conference. 2006. 4150789.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ivković, M, Chilappagari, SK & Vasic, BV 2006, Construction of memory circuits using unreliable components based on low-density parity-check codes. in GLOBECOM - IEEE Global Telecommunications Conference., 4150789, IEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference, San Francisco, CA, United States, 11/27/06. https://doi.org/10.1109/GLOCOM.2006.159
Ivković M, Chilappagari SK, Vasic BV. Construction of memory circuits using unreliable components based on low-density parity-check codes. In GLOBECOM - IEEE Global Telecommunications Conference. 2006. 4150789 https://doi.org/10.1109/GLOCOM.2006.159
Ivković, Miloš ; Chilappagari, Shashi Kiran ; Vasic, Bane V. / Construction of memory circuits using unreliable components based on low-density parity-check codes. GLOBECOM - IEEE Global Telecommunications Conference. 2006.
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