Construction of memory circuits using unreliable components based on low-density parity-check codes

Miloš Ivković, Shashi Kiran Chilappagari, Bane Vasić

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

In this paper, we analyze storage circuits constructed from unreliable memory components. We propose a memory construction, using low-density parity-check codes, based on a construction originally made by Taylor. The storage circuit consists of unreliable memory cells along with a correcting circuit. The correcting circuit is also constructed from unreliable logic gates along with a small number of perfect gates. The modified construction enables the memory device to perform better than the original construction. We present numerical results supporting our claims.

Original languageEnglish (US)
Title of host publicationIEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference
DOIs
StatePublished - Dec 1 2006
EventIEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference - San Francisco, CA, United States
Duration: Nov 27 2006Dec 1 2006

Publication series

NameGLOBECOM - IEEE Global Telecommunications Conference

Other

OtherIEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference
CountryUnited States
CitySan Francisco, CA
Period11/27/0612/1/06

ASJC Scopus subject areas

  • Engineering(all)

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    Ivković, M., Chilappagari, S. K., & Vasić, B. (2006). Construction of memory circuits using unreliable components based on low-density parity-check codes. In IEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference [4150789] (GLOBECOM - IEEE Global Telecommunications Conference). https://doi.org/10.1109/GLOCOM.2006.159