DARPA sensor national testbed

Hardware and software architecture

D. R. Guarino, R. P. Kruger, S. Sayre, T. Sos, C. J. Turner, C Larrabee Winter

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A heterogeneous network of parallel computers developed for complex distributed-processing applications is described. Network computers include a Connection Machine, a Butterfly multiprocessor, a WARP systolic array, and a Symbolics and several SUN workstations. An ethernet and a high-bandwidth APTEC bus support data transfers. Distributed applications are built from individual processes executing on computers in the network. A powerful asynchronous communication facility is built upon the multiple computer operating systems to provide uniform message passing, global memory variables, and remote process execution services to processes. An executive controller and the LISP+ functional language provide a method of integrating distributed processes into an application with transparent control of network resources and communications. Additional applications can be rapidly built from existing processing to support experiments in distributed and parallel applications.

Original languageEnglish (US)
Title of host publicationProc 2nd Symp Front Massively Parallel Comput
Editors Anon
PublisherPubl by IEEE
Pages295-301
Number of pages7
StatePublished - 1988
Externally publishedYes
EventProceedings: The 2nd Symposium on the Frontiers of Massively Parallel Computations - Fairfax, VA, USA
Duration: Oct 10 1988Oct 12 1988

Other

OtherProceedings: The 2nd Symposium on the Frontiers of Massively Parallel Computations
CityFairfax, VA, USA
Period10/10/8810/12/88

Fingerprint

Software architecture
Testbeds
Computer hardware
Sensors
Systolic arrays
Computer operating systems
Communication
Heterogeneous networks
Message passing
Data transfer
Processing
Ethernet
Computer networks
Bandwidth
Data storage equipment
Controllers
Experiments

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Guarino, D. R., Kruger, R. P., Sayre, S., Sos, T., Turner, C. J., & Winter, C. L. (1988). DARPA sensor national testbed: Hardware and software architecture. In Anon (Ed.), Proc 2nd Symp Front Massively Parallel Comput (pp. 295-301). Publ by IEEE.

DARPA sensor national testbed : Hardware and software architecture. / Guarino, D. R.; Kruger, R. P.; Sayre, S.; Sos, T.; Turner, C. J.; Winter, C Larrabee.

Proc 2nd Symp Front Massively Parallel Comput. ed. / Anon. Publ by IEEE, 1988. p. 295-301.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Guarino, DR, Kruger, RP, Sayre, S, Sos, T, Turner, CJ & Winter, CL 1988, DARPA sensor national testbed: Hardware and software architecture. in Anon (ed.), Proc 2nd Symp Front Massively Parallel Comput. Publ by IEEE, pp. 295-301, Proceedings: The 2nd Symposium on the Frontiers of Massively Parallel Computations, Fairfax, VA, USA, 10/10/88.
Guarino DR, Kruger RP, Sayre S, Sos T, Turner CJ, Winter CL. DARPA sensor national testbed: Hardware and software architecture. In Anon, editor, Proc 2nd Symp Front Massively Parallel Comput. Publ by IEEE. 1988. p. 295-301
Guarino, D. R. ; Kruger, R. P. ; Sayre, S. ; Sos, T. ; Turner, C. J. ; Winter, C Larrabee. / DARPA sensor national testbed : Hardware and software architecture. Proc 2nd Symp Front Massively Parallel Comput. editor / Anon. Publ by IEEE, 1988. pp. 295-301
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