Delay uncertainty reduction by gate splitting

Vineet Agarwal, Jin Sun, Meiling Wang

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Traditional timing-variation reduction techniques are only able to decrease gate delay variation by incurring a delay overhead. In this brief, we propose a novel and effective splitting-based variation reduction technique for gates. We developed a new tool called Timing Uncertainty Reduction by Gate Splitting (TURGS), which reduces the timing variations of a circuit and presents little delay overhead at the primary output. Our experimental results show that TURGS achieves up to 20% improvement in timing variation for gates.

Original languageEnglish (US)
Pages (from-to)295-299
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume56
Issue number4
DOIs
StatePublished - 2009

Fingerprint

Uncertainty
Networks (circuits)

Keywords

  • Delay uncertainty reduction
  • Gate cloning
  • Gate split
  • Process variation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Delay uncertainty reduction by gate splitting. / Agarwal, Vineet; Sun, Jin; Wang, Meiling.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 56, No. 4, 2009, p. 295-299.

Research output: Contribution to journalArticle

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