Delay uncertainty reduction by interconnect and gate splitting

Vineet Agarwal, Jin Sun, Alexander Mitev, Janet Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective splitting based variation reduction techniques for both interconnect and gate. We developed a new tool called TURGIS: Timing Uncertainty Reduction by Gate-Interconnect Splitting which reduces the timing variations of a circuit and presents little delay overhead at the primary output. It is shown that using splitting on interconnect can reduce the Chemical-Mechanical Polishing (CMP) induced dishing effect and can result in decrease at an average of 5% in mean interconnect delay in addition to its variation. Improvements of up to 30% are achieved on timing variation for gates of various size while reduction of 55% can be observed in interconnect delay variation.

Original languageEnglish (US)
Title of host publicationProceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Pages690-695
Number of pages6
DOIs
StatePublished - Dec 1 2007
EventASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan
Duration: Jan 23 2007Jan 27 2007

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

OtherASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
CountryJapan
CityYokohama
Period1/23/071/27/07

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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    Agarwal, V., Sun, J., Mitev, A., & Wang, J. (2007). Delay uncertainty reduction by interconnect and gate splitting. In Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 (pp. 690-695). [4196113] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2007.358067