Delay uncertainty reduction by interconnect and gate splitting

Vineet Agarwal, Jin Sun, Alexander Mitev, Meiling Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective splitting based variation reduction techniques for both interconnect and gate. We developed a new tool called TURGIS: Timing Uncertainty Reduction by Gate-Interconnect Splitting which reduces the timing variations of a circuit and presents little delay overhead at the primary output. It is shown that using splitting on interconnect can reduce the Chemical-Mechanical Polishing (CMP) induced dishing effect and can result in decrease at an average of 5% in mean interconnect delay in addition to its variation. Improvements of up to 30% are achieved on timing variation for gates of various size while reduction of 55% can be observed in interconnect delay variation.

Original languageEnglish (US)
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages690-695
Number of pages6
DOIs
StatePublished - 2007
EventASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan
Duration: Jan 23 2007Jan 27 2007

Other

OtherASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
CountryJapan
CityYokohama
Period1/23/071/27/07

Fingerprint

Chemical mechanical polishing
Uncertainty
Networks (circuits)

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Agarwal, V., Sun, J., Mitev, A., & Wang, M. (2007). Delay uncertainty reduction by interconnect and gate splitting. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 690-695). [4196113] https://doi.org/10.1109/ASPDAC.2007.358067

Delay uncertainty reduction by interconnect and gate splitting. / Agarwal, Vineet; Sun, Jin; Mitev, Alexander; Wang, Meiling.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2007. p. 690-695 4196113.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Agarwal, V, Sun, J, Mitev, A & Wang, M 2007, Delay uncertainty reduction by interconnect and gate splitting. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 4196113, pp. 690-695, ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007, Yokohama, Japan, 1/23/07. https://doi.org/10.1109/ASPDAC.2007.358067
Agarwal V, Sun J, Mitev A, Wang M. Delay uncertainty reduction by interconnect and gate splitting. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2007. p. 690-695. 4196113 https://doi.org/10.1109/ASPDAC.2007.358067
Agarwal, Vineet ; Sun, Jin ; Mitev, Alexander ; Wang, Meiling. / Delay uncertainty reduction by interconnect and gate splitting. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2007. pp. 690-695
@inproceedings{5a7b1786c6bc4835b94ecb11b58b3319,
title = "Delay uncertainty reduction by interconnect and gate splitting",
abstract = "Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective splitting based variation reduction techniques for both interconnect and gate. We developed a new tool called TURGIS: Timing Uncertainty Reduction by Gate-Interconnect Splitting which reduces the timing variations of a circuit and presents little delay overhead at the primary output. It is shown that using splitting on interconnect can reduce the Chemical-Mechanical Polishing (CMP) induced dishing effect and can result in decrease at an average of 5{\%} in mean interconnect delay in addition to its variation. Improvements of up to 30{\%} are achieved on timing variation for gates of various size while reduction of 55{\%} can be observed in interconnect delay variation.",
author = "Vineet Agarwal and Jin Sun and Alexander Mitev and Meiling Wang",
year = "2007",
doi = "10.1109/ASPDAC.2007.358067",
language = "English (US)",
isbn = "1424406293",
pages = "690--695",
booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

}

TY - GEN

T1 - Delay uncertainty reduction by interconnect and gate splitting

AU - Agarwal, Vineet

AU - Sun, Jin

AU - Mitev, Alexander

AU - Wang, Meiling

PY - 2007

Y1 - 2007

N2 - Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective splitting based variation reduction techniques for both interconnect and gate. We developed a new tool called TURGIS: Timing Uncertainty Reduction by Gate-Interconnect Splitting which reduces the timing variations of a circuit and presents little delay overhead at the primary output. It is shown that using splitting on interconnect can reduce the Chemical-Mechanical Polishing (CMP) induced dishing effect and can result in decrease at an average of 5% in mean interconnect delay in addition to its variation. Improvements of up to 30% are achieved on timing variation for gates of various size while reduction of 55% can be observed in interconnect delay variation.

AB - Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective splitting based variation reduction techniques for both interconnect and gate. We developed a new tool called TURGIS: Timing Uncertainty Reduction by Gate-Interconnect Splitting which reduces the timing variations of a circuit and presents little delay overhead at the primary output. It is shown that using splitting on interconnect can reduce the Chemical-Mechanical Polishing (CMP) induced dishing effect and can result in decrease at an average of 5% in mean interconnect delay in addition to its variation. Improvements of up to 30% are achieved on timing variation for gates of various size while reduction of 55% can be observed in interconnect delay variation.

UR - http://www.scopus.com/inward/record.url?scp=46649119301&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=46649119301&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2007.358067

DO - 10.1109/ASPDAC.2007.358067

M3 - Conference contribution

AN - SCOPUS:46649119301

SN - 1424406293

SN - 9781424406296

SP - 690

EP - 695

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

ER -