Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture

Avinash Kodi, Ashwini Sarathy, Ahmed Louri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

Network-on-Chip (NoC)architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the ptimization of NoC architectures has shown that the design of buffers in the NoC routers influences the power consumption, area overhead and performance of the entire network. In this paper, we propose a low-power area-efficient NoC architecture by reducing the number of router buffers. As a reduction in the number of buffers degrades the network's performance, we propose to use the existing repeaters along the inter-router links as adaptive channel buffers for storing data when required. We evaluate the proposed adaptive communication channel buffers under static and dynamic buffer allocation in 8 x 8 mesh and folded torus network topologies. Simulation results show that reducing the router buffer size in half and using the adaptive channel buffers reduces the buffer power by 40-52% and leads to a 17-20% savings in overall network power with a 50% reduction in router area. The design with dynamic buffer allocation shows a marginal 1-5% drop in performance, while static buffer allocation shows a 10-20% drop in performance, for various traffic patterns.

Original languageEnglish (US)
Title of host publicationANCS'07 - Proceedings of the 2007 ACM Symposium on Architecture for Networking and Communications
Pages47-56
Number of pages10
DOIs
StatePublished - Dec 1 2007
Event3rd ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS 2007 - Orlando, FL, United States
Duration: Dec 3 2007Dec 4 2007

Publication series

NameANCS'07 - Proceedings of the 2007 ACM Symposium on Architecture for Networking and Communications

Other

Other3rd ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS 2007
CountryUnited States
CityOrlando, FL
Period12/3/0712/4/07

Keywords

  • low-power design
  • network-on-chip

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Kodi, A., Sarathy, A., & Louri, A. (2007). Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture. In ANCS'07 - Proceedings of the 2007 ACM Symposium on Architecture for Networking and Communications (pp. 47-56). (ANCS'07 - Proceedings of the 2007 ACM Symposium on Architecture for Networking and Communications). https://doi.org/10.1145/1323548.1323561