Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs)

Avinash Kodi, Ahmed Louri, Meiling Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

Network-on-chip (NoC) architectures are fast becoming an attractive solution to address the interconnect delay problems in chip multiprocessors (CMPs). However, increased power dissipation and limited performance improvements have hindered the wide-deployment of NoCs. In this paper, we combine two techniques of adaptive channel buffers and router pipeline bypassing to simultaneously reduce power consumption and improve performance. Power consumption can be decreased by reducing the size of the router buffers. However, as reducing router buffers alone will significantly degrade performance, we compensate by utilizing the newly proposed dual-function channel buffers that allow flits to be stored on wires when required. Network bypassing technique, on the other hand, allows flits to bypass the router pipeline and thereby avoid the router buffers altogether. We combine the two techniques and attempt to keep the flits on the wires from source to destination. Our simulation results of the proposed methodology combining the two techniques, yield a overall power reduction of 62% over the baseline and improve performance (throughput and latency) by more than 10%.

Original languageEnglish (US)
Title of host publicationProceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009
Pages826-832
Number of pages7
DOIs
StatePublished - 2009
Event10th International Symposium on Quality Electronic Design, ISQED 2009 - San Jose, CA, United States
Duration: Mar 16 2009Mar 18 2009

Other

Other10th International Symposium on Quality Electronic Design, ISQED 2009
CountryUnited States
CitySan Jose, CA
Period3/16/093/18/09

Fingerprint

Routers
Electric power utilization
Pipelines
Wire
Energy dissipation
Throughput
Network-on-chip

Keywords

  • Channel Buffers
  • Network-on-Chips (NoCs)
  • Router Bypassing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kodi, A., Louri, A., & Wang, M. (2009). Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs). In Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009 (pp. 826-832). [4810399] https://doi.org/10.1109/ISQED.2009.4810399

Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs). / Kodi, Avinash; Louri, Ahmed; Wang, Meiling.

Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009. 2009. p. 826-832 4810399.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kodi, A, Louri, A & Wang, M 2009, Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs). in Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009., 4810399, pp. 826-832, 10th International Symposium on Quality Electronic Design, ISQED 2009, San Jose, CA, United States, 3/16/09. https://doi.org/10.1109/ISQED.2009.4810399
Kodi A, Louri A, Wang M. Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs). In Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009. 2009. p. 826-832. 4810399 https://doi.org/10.1109/ISQED.2009.4810399
Kodi, Avinash ; Louri, Ahmed ; Wang, Meiling. / Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs). Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009. 2009. pp. 826-832
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