Design of low jitter phase-locked loop with closed loop voltage controlled oscillator

Seok Min Jung, Meiling Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

This paper presents a novel phase-locked loop (PLL) architecture to generate a low jitter output clock with a closed loop voltage controlled oscillator (VCO). The proposed closed loop VCO consists of an open loop VCO, an integrator, a non-overlapping clock generator and a switched-capacitor resistor. Because the closed loop VCO has a high-pass characteristic for a VCO noise transfer function and a negative feedback loop suppresses a phase noise of the open loop VCO, the closed loop VCO shows the low phase noise compared to the conventional open loop VCO. Moreover, the closed loop VCO can filter any perturbation at the control voltage due to a low-pass characteristic of input voltage transfer function. We design the proposed PLL scheme in 130 nm low power CMOS technology at 1.5V supply. An integrated RMS jitter is 5.81 psec at 300 MHz output frequency, which is 24% smaller than the jitter of previous PLL with the open loop VCO. The proposed PLL consumes 4.8 mW at 400 MHz output frequency.

Original languageEnglish (US)
Title of host publication2015 IEEE 16th Annual Wireless and Microwave Technology Conference, WAMICON 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479975211
DOIs
StatePublished - Jun 9 2015
Event2015 16th IEEE Annual Wireless and Microwave Technology Conference, WAMICON 2015 - Cocoa Beach, United States
Duration: Apr 13 2015Apr 15 2015

Other

Other2015 16th IEEE Annual Wireless and Microwave Technology Conference, WAMICON 2015
CountryUnited States
CityCocoa Beach
Period4/13/154/15/15

Keywords

  • Jitter
  • Phase noise
  • Phase-locked loop
  • Voltage controlled oscillator

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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