Design space exploration for application specific FPGAs in system-on-a-chip designs

Mark Hammerquist, Roman L Lysecky

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The inclusion of field programmable gate arrays (FPGAs) within a system-on-a-chip (SOC) design offers programmability, flexibility, and reconfigurability not possible with application specific integrated circuits (ASIC) or full-custom implementations. However, these benefits come at the expense of significant area, performance, and power consumption overheads compared to ASIC or full-custom circuits. As a typical SOC design will require fabrication of the final integrated circuit, rather than rely on a generic FPGA architecture, an FPGA integrated within an SOC design can be optimized for the specific intended application. In this paper, we present an initial design space exploration framework for generating an application specific FPGA (ASFPGA) by tailoring several FPGA architectural features for a specific hardware circuit to improve the area, delay, or energy consumption compared to traditional FPGA designs and reduce the overheads of utilizing an FPGA compared to ASIC and full custom implementations.

Original languageEnglish (US)
Title of host publication2008 IEEE International SOC Conference, SOCC
Pages279-282
Number of pages4
DOIs
StatePublished - 2008
Event2008 IEEE International SOC Conference, SOCC - Newport Beach, CA, United States
Duration: Sep 17 2008Sep 20 2008

Other

Other2008 IEEE International SOC Conference, SOCC
CountryUnited States
CityNewport Beach, CA
Period9/17/089/20/08

Fingerprint

Field programmable gate arrays (FPGA)
Application specific integrated circuits
Networks (circuits)
Integrated circuits
Electric power utilization
Energy utilization
Hardware
Fabrication

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Hammerquist, M., & Lysecky, R. L. (2008). Design space exploration for application specific FPGAs in system-on-a-chip designs. In 2008 IEEE International SOC Conference, SOCC (pp. 279-282). [4641527] https://doi.org/10.1109/SOCC.2008.4641527

Design space exploration for application specific FPGAs in system-on-a-chip designs. / Hammerquist, Mark; Lysecky, Roman L.

2008 IEEE International SOC Conference, SOCC. 2008. p. 279-282 4641527.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hammerquist, M & Lysecky, RL 2008, Design space exploration for application specific FPGAs in system-on-a-chip designs. in 2008 IEEE International SOC Conference, SOCC., 4641527, pp. 279-282, 2008 IEEE International SOC Conference, SOCC, Newport Beach, CA, United States, 9/17/08. https://doi.org/10.1109/SOCC.2008.4641527
Hammerquist M, Lysecky RL. Design space exploration for application specific FPGAs in system-on-a-chip designs. In 2008 IEEE International SOC Conference, SOCC. 2008. p. 279-282. 4641527 https://doi.org/10.1109/SOCC.2008.4641527
Hammerquist, Mark ; Lysecky, Roman L. / Design space exploration for application specific FPGAs in system-on-a-chip designs. 2008 IEEE International SOC Conference, SOCC. 2008. pp. 279-282
@inproceedings{1d1078e8a66d4634b6e94edeb1cc5893,
title = "Design space exploration for application specific FPGAs in system-on-a-chip designs",
abstract = "The inclusion of field programmable gate arrays (FPGAs) within a system-on-a-chip (SOC) design offers programmability, flexibility, and reconfigurability not possible with application specific integrated circuits (ASIC) or full-custom implementations. However, these benefits come at the expense of significant area, performance, and power consumption overheads compared to ASIC or full-custom circuits. As a typical SOC design will require fabrication of the final integrated circuit, rather than rely on a generic FPGA architecture, an FPGA integrated within an SOC design can be optimized for the specific intended application. In this paper, we present an initial design space exploration framework for generating an application specific FPGA (ASFPGA) by tailoring several FPGA architectural features for a specific hardware circuit to improve the area, delay, or energy consumption compared to traditional FPGA designs and reduce the overheads of utilizing an FPGA compared to ASIC and full custom implementations.",
author = "Mark Hammerquist and Lysecky, {Roman L}",
year = "2008",
doi = "10.1109/SOCC.2008.4641527",
language = "English (US)",
isbn = "9781424425969",
pages = "279--282",
booktitle = "2008 IEEE International SOC Conference, SOCC",

}

TY - GEN

T1 - Design space exploration for application specific FPGAs in system-on-a-chip designs

AU - Hammerquist, Mark

AU - Lysecky, Roman L

PY - 2008

Y1 - 2008

N2 - The inclusion of field programmable gate arrays (FPGAs) within a system-on-a-chip (SOC) design offers programmability, flexibility, and reconfigurability not possible with application specific integrated circuits (ASIC) or full-custom implementations. However, these benefits come at the expense of significant area, performance, and power consumption overheads compared to ASIC or full-custom circuits. As a typical SOC design will require fabrication of the final integrated circuit, rather than rely on a generic FPGA architecture, an FPGA integrated within an SOC design can be optimized for the specific intended application. In this paper, we present an initial design space exploration framework for generating an application specific FPGA (ASFPGA) by tailoring several FPGA architectural features for a specific hardware circuit to improve the area, delay, or energy consumption compared to traditional FPGA designs and reduce the overheads of utilizing an FPGA compared to ASIC and full custom implementations.

AB - The inclusion of field programmable gate arrays (FPGAs) within a system-on-a-chip (SOC) design offers programmability, flexibility, and reconfigurability not possible with application specific integrated circuits (ASIC) or full-custom implementations. However, these benefits come at the expense of significant area, performance, and power consumption overheads compared to ASIC or full-custom circuits. As a typical SOC design will require fabrication of the final integrated circuit, rather than rely on a generic FPGA architecture, an FPGA integrated within an SOC design can be optimized for the specific intended application. In this paper, we present an initial design space exploration framework for generating an application specific FPGA (ASFPGA) by tailoring several FPGA architectural features for a specific hardware circuit to improve the area, delay, or energy consumption compared to traditional FPGA designs and reduce the overheads of utilizing an FPGA compared to ASIC and full custom implementations.

UR - http://www.scopus.com/inward/record.url?scp=67650273315&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=67650273315&partnerID=8YFLogxK

U2 - 10.1109/SOCC.2008.4641527

DO - 10.1109/SOCC.2008.4641527

M3 - Conference contribution

SN - 9781424425969

SP - 279

EP - 282

BT - 2008 IEEE International SOC Conference, SOCC

ER -