Development of chip model library for the computer-aided analysis of electronic packages

S. N. Pratapneni, C. M. Wolff, P. Hsu, Jerzy W Rozenblit, J. L. Prince

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper discusses the development of a chip model library for the complete design and simulation of Multichip Assemblies. The simulation of the driver/receiver part of the chips mounted in Multichip Modules (MCMs) can be done using a variety of models at varying levels of complexity. A hierarchy is used to organize the models for use with an intelligent model selection tool. Model selection is based on the tradeoff between accuracy and speed. The four models to be considered in this paper are device, table-based, equation based and simple RC models. The basic RC model, a physical model, considers transistor on-resistance and load capacitance as a complete representation of the driver circuit. The table lookup approach stores a detailed transfer function of device operation or circuit operation in a table using a device level circuit simulator. Equation-based models simplify the physical device equations based on the switching behavior of a particular circuit. An integral environment with this group of models is developed with an object oriented approach. Each of the model templates is treated as an object and it can be repeated as required.

Original languageEnglish (US)
Title of host publicationIEEE/CHMT European International Electronic Manufacturing Technology Symposium
Editors Anon
PublisherPubl by IEEE
Pages417-422
Number of pages6
ISBN (Print)0780314247
StatePublished - 1993
EventProceedings of the 15th IEEE/CHMT International Electronics Manufacturing Technology (IEMT) Symposium - Santa Clara, CA, USA
Duration: Oct 4 1993Oct 6 1993

Other

OtherProceedings of the 15th IEEE/CHMT International Electronics Manufacturing Technology (IEMT) Symposium
CitySanta Clara, CA, USA
Period10/4/9310/6/93

Fingerprint

Computer aided analysis
Networks (circuits)
Multichip modules
Table lookup
Transfer functions
Transistors

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Pratapneni, S. N., Wolff, C. M., Hsu, P., Rozenblit, J. W., & Prince, J. L. (1993). Development of chip model library for the computer-aided analysis of electronic packages. In Anon (Ed.), IEEE/CHMT European International Electronic Manufacturing Technology Symposium (pp. 417-422). Publ by IEEE.

Development of chip model library for the computer-aided analysis of electronic packages. / Pratapneni, S. N.; Wolff, C. M.; Hsu, P.; Rozenblit, Jerzy W; Prince, J. L.

IEEE/CHMT European International Electronic Manufacturing Technology Symposium. ed. / Anon. Publ by IEEE, 1993. p. 417-422.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pratapneni, SN, Wolff, CM, Hsu, P, Rozenblit, JW & Prince, JL 1993, Development of chip model library for the computer-aided analysis of electronic packages. in Anon (ed.), IEEE/CHMT European International Electronic Manufacturing Technology Symposium. Publ by IEEE, pp. 417-422, Proceedings of the 15th IEEE/CHMT International Electronics Manufacturing Technology (IEMT) Symposium, Santa Clara, CA, USA, 10/4/93.
Pratapneni SN, Wolff CM, Hsu P, Rozenblit JW, Prince JL. Development of chip model library for the computer-aided analysis of electronic packages. In Anon, editor, IEEE/CHMT European International Electronic Manufacturing Technology Symposium. Publ by IEEE. 1993. p. 417-422
Pratapneni, S. N. ; Wolff, C. M. ; Hsu, P. ; Rozenblit, Jerzy W ; Prince, J. L. / Development of chip model library for the computer-aided analysis of electronic packages. IEEE/CHMT European International Electronic Manufacturing Technology Symposium. editor / Anon. Publ by IEEE, 1993. pp. 417-422
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