Dynamic FPGA routing for just-in-time FPGA compilation

Roman L Lysecky, Frank Vahid, Sheldon X D Tan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

41 Citations (Scopus)

Abstract

Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. However, embedded systems increasingly incorporate Field Programmable Gate Arrays (FPGAs), for which the concept of a standard hardware binary did not previously exist, requiring designers to implement a hardware circuit for a single specific FPGA. We introduce the concept of a standard hardware binary, using a just-in-time compiler to compile the hardware binary to an FPGA. A JIT compiler for FPGAs requires the development of lean versions of technology mapping, placement, and routing algorithms, of which routing is the most computationally and memory expensive step. We present the Riverside On-Chip Router (ROCR) designed to efficiently route a hardware circuit for a simple configurable logic fabric that we have developed. Through experiments with MCNC benchmark hardware circuits, we show that ROCR works well for JIT FPGA compilation, producing good hardware circuits using an order of magnitude less memory resources and execution time compared with the well known Versatile Place and Route (VPR) tool suite. ROCR produces good hardware circuits using 13X less memory and executing 10X faster than VPR's fastest routing algorithm. Furthermore, our results show ROCR requires only 10% additional routing resources, and results in circuit speeds only 32% slower than VPR's timing-driven router, and speeds that are actually 10% faster than VPR's routability-driven router.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages954-959
Number of pages6
StatePublished - 2004
Externally publishedYes
EventProceedings of the 41st Design Automation Conference - San Diego, CA, United States
Duration: Jun 7 2004Jun 11 2004

Other

OtherProceedings of the 41st Design Automation Conference
CountryUnited States
CitySan Diego, CA
Period6/7/046/11/04

Fingerprint

Routers
Field programmable gate arrays (FPGA)
Hardware
Networks (circuits)
Routing algorithms
Data storage equipment
Computer hardware
Embedded systems
Experiments

Keywords

  • Codesign
  • Configurable logic
  • Dynamic optimization
  • FPGA
  • Hardware/software partitioning
  • Just-in-time compilation
  • Place and route
  • Platforms
  • System-on-a-chip
  • Warp processors

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Lysecky, R. L., Vahid, F., & Tan, S. X. D. (2004). Dynamic FPGA routing for just-in-time FPGA compilation. In Proceedings - Design Automation Conference (pp. 954-959)

Dynamic FPGA routing for just-in-time FPGA compilation. / Lysecky, Roman L; Vahid, Frank; Tan, Sheldon X D.

Proceedings - Design Automation Conference. 2004. p. 954-959.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lysecky, RL, Vahid, F & Tan, SXD 2004, Dynamic FPGA routing for just-in-time FPGA compilation. in Proceedings - Design Automation Conference. pp. 954-959, Proceedings of the 41st Design Automation Conference, San Diego, CA, United States, 6/7/04.
Lysecky RL, Vahid F, Tan SXD. Dynamic FPGA routing for just-in-time FPGA compilation. In Proceedings - Design Automation Conference. 2004. p. 954-959
Lysecky, Roman L ; Vahid, Frank ; Tan, Sheldon X D. / Dynamic FPGA routing for just-in-time FPGA compilation. Proceedings - Design Automation Conference. 2004. pp. 954-959
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