Dynamic reconfiguration of 3D photonic networks-on-chip for maximizing performance and improving fault tolerance

Randy Morris, Avinash Karanth Kodi, Ahmed Louri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Abstract

As power dissipation in future Networks-on-Chips (NoCs) is projected to be a major bottleneck, researchers are actively engaged in developing alternate power-efficient technology solutions. Photonic interconnects is a disruptive technology solution that is capable of delivering the communication bandwidth at low power dissipation when the number of cores is scaled to large numbers. Similarly, 3D stacking is another interconnect technology solution that can lead to low energy/bit for communication. In this paper, we propose to combine photonic interconnects with 3D stacking to develop a scalable, reconfigurable, power-efficient and high-performance interconnect for future many-core systems, called R-3PO (Reconfigurable 3DPhotonic Networks-on-Chip). We propose to develop a multi-layer photonic interconnect that can dynamically reconfigure without system intervention and allocate channel bandwidth from less utilized links to more utilized communication links. In addition to improving performance, reconfiguration can re-allocate bandwidth around faulty channels, thereby increasing the resiliency of the architecture and gracefully degrading performance. For 64-core reconfigured network, our simulation results indicate that the performance can be further improved by 10%-25% for Splash-2, PARSEC and SPEC CPU2006 benchmarks, where as simulation results for 256-core chip indicate a performance improvement of more than 25% while saving 6%-36% energy when compared to state-of-the-art on-chip electrical and optical networks.

Original languageEnglish (US)
Title of host publicationProceedings - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012
Pages282-293
Number of pages12
DOIs
StatePublished - 2012
Event2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012 - Vancouver, BC, Canada
Duration: Dec 1 2012Dec 5 2012

Other

Other2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012
CountryCanada
CityVancouver, BC
Period12/1/1212/5/12

Fingerprint

Fault tolerance
Photonics
Bandwidth
Telecommunication links
Energy dissipation
Communication
Fiber optic networks
Network-on-chip

Keywords

  • Fault Tolerance
  • Networks-on-Chip (NoC)
  • Photonic
  • Reconfiguration

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Morris, R., Kodi, A. K., & Louri, A. (2012). Dynamic reconfiguration of 3D photonic networks-on-chip for maximizing performance and improving fault tolerance. In Proceedings - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012 (pp. 282-293). [6493627] https://doi.org/10.1109/MICRO.2012.34

Dynamic reconfiguration of 3D photonic networks-on-chip for maximizing performance and improving fault tolerance. / Morris, Randy; Kodi, Avinash Karanth; Louri, Ahmed.

Proceedings - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012. 2012. p. 282-293 6493627.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Morris, R, Kodi, AK & Louri, A 2012, Dynamic reconfiguration of 3D photonic networks-on-chip for maximizing performance and improving fault tolerance. in Proceedings - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012., 6493627, pp. 282-293, 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012, Vancouver, BC, Canada, 12/1/12. https://doi.org/10.1109/MICRO.2012.34
Morris R, Kodi AK, Louri A. Dynamic reconfiguration of 3D photonic networks-on-chip for maximizing performance and improving fault tolerance. In Proceedings - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012. 2012. p. 282-293. 6493627 https://doi.org/10.1109/MICRO.2012.34
Morris, Randy ; Kodi, Avinash Karanth ; Louri, Ahmed. / Dynamic reconfiguration of 3D photonic networks-on-chip for maximizing performance and improving fault tolerance. Proceedings - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012. 2012. pp. 282-293
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