Early assessment of leakage power for system level design

C. Talarico, B. Pillilli, K. L. Vakati, J. M. Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper presents a system level methodology for analyzing leakage power in the early stages of a system design. The assessment of leakage takes into account the simultaneous effect of threshold-voltage (Vt), oxide thickness (t/sub ox/), device width (W), the inputs applied and statistical process variations. The approach has been validated by applying it to the design of a digital signal processing system. The results indicate that our power estimation technique is within 10% of SPICE, with the benefit of executing 15/spl times/ faster.

Original languageEnglish (US)
Title of host publicationProceedings - 6th International Symposium on Quality Electronic Design, ISQED 2005
Pages133-136
Number of pages4
DOIs
StatePublished - Dec 1 2005
Event6th International Symposium on Quality Electronic Design, ISQED 2005 - San Jose, CA, United States
Duration: Mar 21 2005Mar 23 2005

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other6th International Symposium on Quality Electronic Design, ISQED 2005
CountryUnited States
CitySan Jose, CA
Period3/21/053/23/05

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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    Talarico, C., Pillilli, B., Vakati, K. L., & Wang, J. M. (2005). Early assessment of leakage power for system level design. In Proceedings - 6th International Symposium on Quality Electronic Design, ISQED 2005 (pp. 133-136). [1410571] (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2005.50