Effect of pad micro-texture on frictional force, removal rate, and wafer topography during copper CMP process

Y. Zhuang, X. Liao, L. J. Borucki, S. Theng, X. Wei, T. Ashizawa, A. Philipossian

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

In this study, the effect of pad micro-texture on frictional force, removal rate, and wafer topography during copper CMP process was investigated. 200-mm blanket copper wafers and Sematech854 patterned wafers were polished and pad samples were taken after wafer polishing. Pad contact area and surface topography were analyzed using a laser confocal microscope. The Mitsubishi Materials Corporation (MMC) 100-grit TRD disc generated much larger flat near contact areas that corresponded to conditioning debris and fractured/collapsed pore walls. The conditioning debris and fractured/collapsed pore walls partly covered the adjacent pores, making the pad surface more lubricated and rendering a lower coefficient of friction and removal rate compared with the 3M A2810 disc. The mean summit curvature generated by the MMC disc was larger than the 3M disc during patterned wafer polishing, indicating sharper pad summits contributed to higher dishing for the MMC disc.

Original languageEnglish (US)
Title of host publicationChina Semiconductor Technology International Conference 2010, CSTIC 2010
Pages599-604
Number of pages6
Edition1
DOIs
StatePublished - Dec 1 2010
EventChina Semiconductor Technology International Conference 2010, CSTIC 2010 - Shanghai, China
Duration: Mar 18 2010Mar 19 2010

Publication series

NameECS Transactions
Number1
Volume27
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherChina Semiconductor Technology International Conference 2010, CSTIC 2010
CountryChina
CityShanghai
Period3/18/103/19/10

ASJC Scopus subject areas

  • Engineering(all)

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    Zhuang, Y., Liao, X., Borucki, L. J., Theng, S., Wei, X., Ashizawa, T., & Philipossian, A. (2010). Effect of pad micro-texture on frictional force, removal rate, and wafer topography during copper CMP process. In China Semiconductor Technology International Conference 2010, CSTIC 2010 (1 ed., pp. 599-604). (ECS Transactions; Vol. 27, No. 1). https://doi.org/10.1149/1.3360681