Effects of technology mapping on fault-detection coverage in reprogrammable FPGAs

K. Kwiat, W. Debany, Salim A Hariri

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

Although field-programmable gate arrays (FPGAs) are tested by their manufacturers prior to shipment, they are still susceptible to failures in the field. In this paper test vectors generated for the emulated (i.e. mission) circuit are fault-simulated on two different models: the original view of the circuit, and the design as it is mapped to the FPGA's logic cells. Faults in the cells and in the programming logic are considered. Experiments show that this commonly-used approach fails to detect most of the faults in the FPGA.

Original languageEnglish (US)
Pages (from-to)407-410
Number of pages4
JournalIEE Proceedings: Computers and Digital Techniques
Volume142
Issue number6
DOIs
StatePublished - Nov 1995
Externally publishedYes

Fingerprint

Fault Detection
Fault detection
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Coverage
Fault
Logic programming
Networks (circuits)
Cell
Logic Programming
Logic
Experiment
Experiments
Model

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Hardware and Architecture
  • Theoretical Computer Science

Cite this

Effects of technology mapping on fault-detection coverage in reprogrammable FPGAs. / Kwiat, K.; Debany, W.; Hariri, Salim A.

In: IEE Proceedings: Computers and Digital Techniques, Vol. 142, No. 6, 11.1995, p. 407-410.

Research output: Contribution to journalArticle

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