Although field-programmable gate arrays (FPGAs) are tested by their manufacturers prior to shipment, they are still susceptible to failures in the field. In this paper test vectors generated for the emulated (i.e. mission) circuit are fault-simulated on two different models: the original view of the circuit, and the design as it is mapped to the FPGA's logic cells. Faults in the cells and in the programming logic are considered. Experiments show that this commonly-used approach fails to detect most of the faults in the FPGA.
ASJC Scopus subject areas
- Computational Theory and Mathematics
- Hardware and Architecture
- Theoretical Computer Science