Efficient FPGA implementation of probabilistic gallager B LDPC decoder

Fakhreddine Ghaffari, Burak Unal, Ali Akoglu, Khoa Le, David Declercq, Bane V Vasic

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper presents the performance evaluation of the Probabilistic Gallager B (PGaB), a hard decision message passing Low Density Parity Check (LDPC) Decoder, with respect to the soft decision based decoders MinSum (MS) and Offset-MinSum (OMS). PGaB algorithm relies on introducing deliberate and controlled randomness to some of the exchanged messages of the GaB decoder such that it is able to escape from local minima associated with dominant trapping sets. We show that PGaB delivers higher decoding throughput than soft decision based decoders MS and OMS while using much fewer amount of Field Programmable Gate Array (FPGA) resources. Our Monte-Carlo simulation results show that the decoding performance of the PGaB on Binary Symmetric Channel (BSC) is far better than the deterministic GaB and very close to MS and OMS performances especially in error floor region.

Original languageEnglish (US)
Title of host publicationICECS 2017 - 24th IEEE International Conference on Electronics, Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages178-181
Number of pages4
Volume2018-January
ISBN (Electronic)9781538619117
DOIs
Publication statusPublished - Feb 14 2018
Event24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017 - Batumi, Georgia
Duration: Dec 5 2017Dec 8 2017

Other

Other24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017
CountryGeorgia
CityBatumi
Period12/5/1712/8/17

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Keywords

  • FPGA architecture
  • hardware complexity/decoding performance trade-off
  • high-performance probabilistic hard-decision LDPC decoders

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Energy Engineering and Power Technology

Cite this

Ghaffari, F., Unal, B., Akoglu, A., Le, K., Declercq, D., & Vasic, B. V. (2018). Efficient FPGA implementation of probabilistic gallager B LDPC decoder. In ICECS 2017 - 24th IEEE International Conference on Electronics, Circuits and Systems (Vol. 2018-January, pp. 178-181). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2017.8292048