Abstract
In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. In [2], the authors show that using randomness in bit-flipping decoders can greatly improve the error correction performance. In this paper, two models of random generators are proposed and compared through hardware implementation and performance simulation. A conventional implementation of the random generator through LFSR as a first design, and a new approach using binary sequences that are produced by the LDPC decoder, named IVRG, as second design. We show that both implementation of the PGDBF improve greatly the error correction performance, while maintaining the same large throughtput. However, the performance gain requires a large hardware overhead in the case of LFSR-PGDBF, while the overhead is limited to only 10% in the case of the IVRG-PGDBF.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1494-1497 |
| Number of pages | 4 |
| Volume | 2015-July |
| ISBN (Print) | 9781479983919 |
| DOIs | |
| State | Published - Jul 27 2015 |
| Event | IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: May 24 2015 → May 27 2015 |
Other
| Other | IEEE International Symposium on Circuits and Systems, ISCAS 2015 |
|---|---|
| Country | Portugal |
| City | Lisbon |
| Period | 5/24/15 → 5/27/15 |
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Keywords
- bit-flipping
- LDPC decoders
- PGDBF
- random generators
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Efficient realization of probabilistic gradient descent bit flipping decoders. / Le, Khoa; Declercq, David; Ghaffari, Fakhreddine; Spagnol, Christian; Popovici, Emmanuel; Ivanis, Predrag; Vasic, Bane V.
Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. p. 1494-1497 7168928.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Efficient realization of probabilistic gradient descent bit flipping decoders
AU - Le, Khoa
AU - Declercq, David
AU - Ghaffari, Fakhreddine
AU - Spagnol, Christian
AU - Popovici, Emmanuel
AU - Ivanis, Predrag
AU - Vasic, Bane V
PY - 2015/7/27
Y1 - 2015/7/27
N2 - In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. In [2], the authors show that using randomness in bit-flipping decoders can greatly improve the error correction performance. In this paper, two models of random generators are proposed and compared through hardware implementation and performance simulation. A conventional implementation of the random generator through LFSR as a first design, and a new approach using binary sequences that are produced by the LDPC decoder, named IVRG, as second design. We show that both implementation of the PGDBF improve greatly the error correction performance, while maintaining the same large throughtput. However, the performance gain requires a large hardware overhead in the case of LFSR-PGDBF, while the overhead is limited to only 10% in the case of the IVRG-PGDBF.
AB - In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. In [2], the authors show that using randomness in bit-flipping decoders can greatly improve the error correction performance. In this paper, two models of random generators are proposed and compared through hardware implementation and performance simulation. A conventional implementation of the random generator through LFSR as a first design, and a new approach using binary sequences that are produced by the LDPC decoder, named IVRG, as second design. We show that both implementation of the PGDBF improve greatly the error correction performance, while maintaining the same large throughtput. However, the performance gain requires a large hardware overhead in the case of LFSR-PGDBF, while the overhead is limited to only 10% in the case of the IVRG-PGDBF.
KW - bit-flipping
KW - LDPC decoders
KW - PGDBF
KW - random generators
UR - http://www.scopus.com/inward/record.url?scp=84946203171&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84946203171&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2015.7168928
DO - 10.1109/ISCAS.2015.7168928
M3 - Conference contribution
SN - 9781479983919
VL - 2015-July
SP - 1494
EP - 1497
BT - Proceedings - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
ER -