Efficient realization of probabilistic gradient descent bit flipping decoders

Khoa Le, David Declercq, Fakhreddine Ghaffari, Christian Spagnol, Emmanuel Popovici, Predrag Ivanis, Bane V Vasic

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. In [2], the authors show that using randomness in bit-flipping decoders can greatly improve the error correction performance. In this paper, two models of random generators are proposed and compared through hardware implementation and performance simulation. A conventional implementation of the random generator through LFSR as a first design, and a new approach using binary sequences that are produced by the LDPC decoder, named IVRG, as second design. We show that both implementation of the PGDBF improve greatly the error correction performance, while maintaining the same large throughtput. However, the performance gain requires a large hardware overhead in the case of LFSR-PGDBF, while the overhead is limited to only 10% in the case of the IVRG-PGDBF.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1494-1497
Number of pages4
Volume2015-July
ISBN (Print)9781479983919
DOIs
StatePublished - Jul 27 2015
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: May 24 2015May 27 2015

Other

OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
CountryPortugal
CityLisbon
Period5/24/155/27/15

Fingerprint

Error correction
Hardware
Binary sequences

Keywords

  • bit-flipping
  • LDPC decoders
  • PGDBF
  • random generators

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Le, K., Declercq, D., Ghaffari, F., Spagnol, C., Popovici, E., Ivanis, P., & Vasic, B. V. (2015). Efficient realization of probabilistic gradient descent bit flipping decoders. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 2015-July, pp. 1494-1497). [7168928] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7168928

Efficient realization of probabilistic gradient descent bit flipping decoders. / Le, Khoa; Declercq, David; Ghaffari, Fakhreddine; Spagnol, Christian; Popovici, Emmanuel; Ivanis, Predrag; Vasic, Bane V.

Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. p. 1494-1497 7168928.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Le, K, Declercq, D, Ghaffari, F, Spagnol, C, Popovici, E, Ivanis, P & Vasic, BV 2015, Efficient realization of probabilistic gradient descent bit flipping decoders. in Proceedings - IEEE International Symposium on Circuits and Systems. vol. 2015-July, 7168928, Institute of Electrical and Electronics Engineers Inc., pp. 1494-1497, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 5/24/15. https://doi.org/10.1109/ISCAS.2015.7168928
Le K, Declercq D, Ghaffari F, Spagnol C, Popovici E, Ivanis P et al. Efficient realization of probabilistic gradient descent bit flipping decoders. In Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July. Institute of Electrical and Electronics Engineers Inc. 2015. p. 1494-1497. 7168928 https://doi.org/10.1109/ISCAS.2015.7168928
Le, Khoa ; Declercq, David ; Ghaffari, Fakhreddine ; Spagnol, Christian ; Popovici, Emmanuel ; Ivanis, Predrag ; Vasic, Bane V. / Efficient realization of probabilistic gradient descent bit flipping decoders. Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. pp. 1494-1497
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