Efficient realization of probabilistic gradient descent bit flipping decoders

Khoa Le, David Declercq, Fakhreddine Ghaffari, Christian Spagnol, Emmanuel Popovici, Predrag Ivanis, Bane V Vasic

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations


In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. In [2], the authors show that using randomness in bit-flipping decoders can greatly improve the error correction performance. In this paper, two models of random generators are proposed and compared through hardware implementation and performance simulation. A conventional implementation of the random generator through LFSR as a first design, and a new approach using binary sequences that are produced by the LDPC decoder, named IVRG, as second design. We show that both implementation of the PGDBF improve greatly the error correction performance, while maintaining the same large throughtput. However, the performance gain requires a large hardware overhead in the case of LFSR-PGDBF, while the overhead is limited to only 10% in the case of the IVRG-PGDBF.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Print)9781479983919
StatePublished - Jul 27 2015
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: May 24 2015May 27 2015


OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015


  • bit-flipping
  • LDPC decoders
  • random generators

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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