Efficient statistical capacitance variability modeling with orthogonal principle factor analysis

Rong Jiang, Wenyin Fu, Meiling Wang, Vince Lin, Charlie Chung Ping Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

22 Citations (Scopus)

Abstract

Due to the ever-increasing complexity of VLSI designs and IC process technologies, the mismatch between a circuit fabricated on the wafer and the one designed in the layout tool grows ever larger. Therefore, characterizing and modeling process variations of interconnect geometry has become an integral part of analysis and optimization of modern VLSI designs. In this paper, we present a systematic methodology to develop a closed form capacitance model, which accurately captures the nonlinear relationship between parasitic capacitances and dominant global/local process variation parameters. The explicit capacitance representation applies the orthogonal principle factor analysis to greatly reduce the number of random variables associated with modeling conductor surface fluctuations while preserving the dominant sources of variations, and consequently the variational capacitance model can be efficiently utilized by statistical model order reduction and timing analysis tools. Experimental results demonstrate that the proposed method exhibits over 100× speedup compared with Monte Carlo simulation while having the advantage of generating explicit variational parasitic capacitance models of high order accuracy.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Pages682-689
Number of pages8
Volume2005
DOIs
StatePublished - 2005
EventICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005 - San Jose, CA, United States
Duration: Nov 6 2005Nov 10 2005

Other

OtherICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005
CountryUnited States
CitySan Jose, CA
Period11/6/0511/10/05

Fingerprint

Factor analysis
Capacitance
Random variables
Geometry
Networks (circuits)

Keywords

  • Capacitance
  • Parasitic extraction
  • Principle factor analysis
  • Process variations
  • Random variable reduction

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Jiang, R., Fu, W., Wang, M., Lin, V., & Chen, C. C. P. (2005). Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD (Vol. 2005, pp. 682-689). [1560153] https://doi.org/10.1109/ICCAD.2005.1560153

Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. / Jiang, Rong; Fu, Wenyin; Wang, Meiling; Lin, Vince; Chen, Charlie Chung Ping.

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. Vol. 2005 2005. p. 682-689 1560153.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Jiang, R, Fu, W, Wang, M, Lin, V & Chen, CCP 2005, Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. vol. 2005, 1560153, pp. 682-689, ICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005, San Jose, CA, United States, 11/6/05. https://doi.org/10.1109/ICCAD.2005.1560153
Jiang R, Fu W, Wang M, Lin V, Chen CCP. Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. Vol. 2005. 2005. p. 682-689. 1560153 https://doi.org/10.1109/ICCAD.2005.1560153
Jiang, Rong ; Fu, Wenyin ; Wang, Meiling ; Lin, Vince ; Chen, Charlie Chung Ping. / Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. Vol. 2005 2005. pp. 682-689
@inproceedings{dadec8b6d21f400bb6c03b4e52b742be,
title = "Efficient statistical capacitance variability modeling with orthogonal principle factor analysis",
abstract = "Due to the ever-increasing complexity of VLSI designs and IC process technologies, the mismatch between a circuit fabricated on the wafer and the one designed in the layout tool grows ever larger. Therefore, characterizing and modeling process variations of interconnect geometry has become an integral part of analysis and optimization of modern VLSI designs. In this paper, we present a systematic methodology to develop a closed form capacitance model, which accurately captures the nonlinear relationship between parasitic capacitances and dominant global/local process variation parameters. The explicit capacitance representation applies the orthogonal principle factor analysis to greatly reduce the number of random variables associated with modeling conductor surface fluctuations while preserving the dominant sources of variations, and consequently the variational capacitance model can be efficiently utilized by statistical model order reduction and timing analysis tools. Experimental results demonstrate that the proposed method exhibits over 100× speedup compared with Monte Carlo simulation while having the advantage of generating explicit variational parasitic capacitance models of high order accuracy.",
keywords = "Capacitance, Parasitic extraction, Principle factor analysis, Process variations, Random variable reduction",
author = "Rong Jiang and Wenyin Fu and Meiling Wang and Vince Lin and Chen, {Charlie Chung Ping}",
year = "2005",
doi = "10.1109/ICCAD.2005.1560153",
language = "English (US)",
isbn = "078039254X",
volume = "2005",
pages = "682--689",
booktitle = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD",

}

TY - GEN

T1 - Efficient statistical capacitance variability modeling with orthogonal principle factor analysis

AU - Jiang, Rong

AU - Fu, Wenyin

AU - Wang, Meiling

AU - Lin, Vince

AU - Chen, Charlie Chung Ping

PY - 2005

Y1 - 2005

N2 - Due to the ever-increasing complexity of VLSI designs and IC process technologies, the mismatch between a circuit fabricated on the wafer and the one designed in the layout tool grows ever larger. Therefore, characterizing and modeling process variations of interconnect geometry has become an integral part of analysis and optimization of modern VLSI designs. In this paper, we present a systematic methodology to develop a closed form capacitance model, which accurately captures the nonlinear relationship between parasitic capacitances and dominant global/local process variation parameters. The explicit capacitance representation applies the orthogonal principle factor analysis to greatly reduce the number of random variables associated with modeling conductor surface fluctuations while preserving the dominant sources of variations, and consequently the variational capacitance model can be efficiently utilized by statistical model order reduction and timing analysis tools. Experimental results demonstrate that the proposed method exhibits over 100× speedup compared with Monte Carlo simulation while having the advantage of generating explicit variational parasitic capacitance models of high order accuracy.

AB - Due to the ever-increasing complexity of VLSI designs and IC process technologies, the mismatch between a circuit fabricated on the wafer and the one designed in the layout tool grows ever larger. Therefore, characterizing and modeling process variations of interconnect geometry has become an integral part of analysis and optimization of modern VLSI designs. In this paper, we present a systematic methodology to develop a closed form capacitance model, which accurately captures the nonlinear relationship between parasitic capacitances and dominant global/local process variation parameters. The explicit capacitance representation applies the orthogonal principle factor analysis to greatly reduce the number of random variables associated with modeling conductor surface fluctuations while preserving the dominant sources of variations, and consequently the variational capacitance model can be efficiently utilized by statistical model order reduction and timing analysis tools. Experimental results demonstrate that the proposed method exhibits over 100× speedup compared with Monte Carlo simulation while having the advantage of generating explicit variational parasitic capacitance models of high order accuracy.

KW - Capacitance

KW - Parasitic extraction

KW - Principle factor analysis

KW - Process variations

KW - Random variable reduction

UR - http://www.scopus.com/inward/record.url?scp=33751418350&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33751418350&partnerID=8YFLogxK

U2 - 10.1109/ICCAD.2005.1560153

DO - 10.1109/ICCAD.2005.1560153

M3 - Conference contribution

SN - 078039254X

SN - 9780780392540

VL - 2005

SP - 682

EP - 689

BT - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

ER -