Evaluating the scalability and performance of 3D stacked reconfigurable nanophotonic interconnects

Randy Morris, Avinash Kodi, Ahmed Louri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

As we integrate hundreds of cores in the future, energy-efficiency and scalability of Network-on-Chips (NoCs) has become a critical challenge. In order to achieve higher performance-per-Watt than traditional metallic interconnects, researchers are exploring alternate energy-effident emerging technology solutions. In this paper, we propose to combine two emerging technologies, namely 3D stacking and nanophotonics that can deliver high on-chip bandwidth and low energy/bit to achieve a high-throughput, reconfigurable and scalable NoC for many-core systems. Our simulation results indicate that the execution time can be reduced up to 25% and energy consumption reduced by 23% for Splash-2, PARSEC, SPEC CPU2006 and synthetic benchmarks for 64-core and 256-core versions.

Original languageEnglish (US)
Title of host publication2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013
PublisherAssociation for Computing Machinery
ISBN (Print)9781467361736
DOIs
StatePublished - Jan 1 2013
Event2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013 - Austin, TX, United States
Duration: Jun 2 2013Jun 2 2013

Publication series

NameInternational Workshop on System Level Interconnect Prediction, SLIP

Other

Other2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013
CountryUnited States
CityAustin, TX
Period6/2/136/2/13

Keywords

  • Nanophotonics
  • NoCs
  • Reconfiguration

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Applied Mathematics

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