Evaluation of fault tolerant channel buffers for improving reliability in NoCs

Dominic DiTomaso, Travis Boraten, Avinash Kodi, Ahmed Louri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Elastic or channel buffers can improve the overall power and area overhead of Network-on-Chip (NoC) architectures by reducing or replacing large, power hungry router buffers. In this paper, we design three fault tolerant schemes for our channel buffers which are used in a concentrated torus (CTorus) topology to reduce power consumption and improve throughput and latency. Our proposed fault tolerant techniques on CTorus topology are evaluated using the Synopsys Design Compiler and our results show (i) an improvement in energy-delay product (EDP) ranging from 20% to 43%, (ii) improvement in saturation throughput of 32% and (iii) an overall reduction in area overhead by 53-68% over other state-of-the-art electrical topologies.

Original languageEnglish (US)
Title of host publication2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
Pages182-185
Number of pages4
DOIs
StatePublished - Oct 16 2012
Event2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012 - Boise, ID, United States
Duration: Aug 5 2012Aug 8 2012

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
CountryUnited States
CityBoise, ID
Period8/5/128/8/12

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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