EZ-Pass: An Energy & Performance-Efficient Power-gating Router Architecture for Scalable NoCs

Hao Zheng, Ahmed Louri

Research output: Contribution to journalArticle

9 Scopus citations


With the technology scaling into nanometer regime, static power is becoming the dominant factor in the overall power consumption of Network-on-Chips (NoCs). Static power can be reduced by powering off routers during consecutive idle time through power-gating techniques. However, power-gating techniques suffer from a large wake-up latency to wake up the powered-off routers. Recent research aims to hide the wake-up latency through early wake-up techniques. However, these techniques do not exploit the full advantage of power-gating due to the early wake-up. Consequently, they do not achieve significant power savings. In this paper, we propose an architecture called Easy Pass (EZ-Pass) router that remedies the large latency overheads while providing significant static power savings. The proposed architecture utilizes idle resources in the network interface to transmit packets without waking the router up. Additionally, the technique hides the wake-up latency by continuing to provide packet transmission during the wake-up phase. We use full system simulation to evaluate our EZ-Pass router on a 64-core NoC with a mesh topology using PARSEC benchmark suites. Our results show that the proposed router reduces static power by up to 31% and overall network latency by up to 32% as compared to early-wakeup optimized power-gating techniques.

Original languageEnglish (US)
JournalIEEE Computer Architecture Letters
StateAccepted/In press - Dec 14 2017
Externally publishedYes


  • Computer architecture
  • Energy-efficient
  • Latches
  • Nework-on-Chips
  • Nickel
  • Ports (Computers)
  • Power-gating
  • Routing
  • Routing protocols
  • Switches

ASJC Scopus subject areas

  • Hardware and Architecture

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