Failure analysis of two-bit flipping decoding algorithms

Bane V Vasic, Dung Viet Nguyen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

We consider a class of bit flipping algorithms for low-density parity-check codes over the binary symmetric channel in which one additional bit at a variable and check nodes is employed. For these two-bit flipping algorithms, we give and illustrate through examples a recursive procedure for finding all uncorrectable error patters and corresponding induced subgraphs, referred as a trapping set profile. This procedure is used to select a small collection of good algorithms that in a decoding diversity approach, run in parallel or serial, outperform Gallager A/B, min-sum and sum product algorithm in the error floor region.

Original languageEnglish (US)
Title of host publication2014 International Conference on Signal Processing and Communications, SPCOM 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479946655
DOIs
Publication statusPublished - Dec 12 2014
Event10th International Conference on Signal Processing and Communications, SPCOM 2014 - Bangalore, India
Duration: Jul 22 2014Jul 25 2014

Other

Other10th International Conference on Signal Processing and Communications, SPCOM 2014
CountryIndia
CityBangalore
Period7/22/147/25/14

    Fingerprint

Keywords

  • Bit flipping algorithms
  • error floor
  • low-density parity-check codes
  • trapping set

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Signal Processing

Cite this

Vasic, B. V., & Nguyen, D. V. (2014). Failure analysis of two-bit flipping decoding algorithms. In 2014 International Conference on Signal Processing and Communications, SPCOM 2014 [6983914] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SPCOM.2014.6983914