Fault tolerant memories based on expander graphs

Shashi Kiran Chilappagari, Bane Vasić

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Scopus citations

Abstract

In this paper we consider memories built from components subject to transient faults. We propose a fault-tolerant memory architecture based on LDPC codes and show the existence of memories which can tolerate constant fraction of failures in all the components. Our proof relies on the expansion property of the underlying Tanner graph of the code. We illustrate our results with specific numerical examples.

Original languageEnglish (US)
Title of host publication2007 IEEE Information Theory Workshop, ITW 2007, Proceedings
Pages126-131
Number of pages6
DOIs
StatePublished - Dec 1 2007
Event2007 IEEE Information Theory Workshop, ITW 2007 - Lake Tahoe, CA, United States
Duration: Sep 2 2007Sep 6 2007

Publication series

Name2007 IEEE Information Theory Workshop, ITW 2007, Proceedings

Other

Other2007 IEEE Information Theory Workshop, ITW 2007
CountryUnited States
CityLake Tahoe, CA
Period9/2/079/6/07

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Information Systems
  • Information Systems and Management

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