Finite-point gate model for fast timing and power analysis

Dinesh Ganesan, Alex Mitev, Janet Wang, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

This paper proposes a new finite-point based approach for efficient characterization of CMOS gate. The new method identifies several key points on the I-V and Q-V curves to define the behavior of the static CMOS gate. It targets performance metrics such as timing, short-circuit power and leakage in the presence of process variations. Experimental results validate the accuracy of the new approach and yields simulation speeds more than 15X faster than BSIM based library characterization.

Original languageEnglish (US)
Title of host publicationProceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008
Pages657-662
Number of pages6
DOIs
StatePublished - Aug 25 2008
Event9th International Symposium on Quality Electronic Design, ISQED 2008 - San Jose, CA, United States
Duration: Mar 17 2008Mar 19 2008

Publication series

NameProceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Other

Other9th International Symposium on Quality Electronic Design, ISQED 2008
CountryUnited States
CitySan Jose, CA
Period3/17/083/19/08

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Ganesan, D., Mitev, A., Wang, J., & Cao, Y. (2008). Finite-point gate model for fast timing and power analysis. In Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008 (pp. 657-662). [4479815] (Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008). https://doi.org/10.1109/ISQED.2008.4479815