Finite-point method for efficient timing characterization of sequential elements

Anupama R. Subramaniam, Janet Roveda, Yu Cao

Research output: Contribution to journalArticlepeer-review

Abstract

Timing characterization of sequential elements, such as latches and flip-flops, is one of the critical steps for timing closure in the pipelined design. Traditional characterization of setup and hold time constraints is computationally intensive, due to the demand on high accuracy in monitoring the operation failure. To improve the efficiency, this work proposes a finite-point based method for the characterization of setup and hold time constraints. The finite-point method identifies several critical data points in the non-linear curve of timing characteristics, and abstracts the essential setup/hold information from them. Moreover, compact models are derived for each point, further reducing the computation cost. The proposed method is general for all sequential elements in the standard cell library. It is comprehensively validated using benchmark circuits at 45 nm node. Experimental results demonstrate approximately 25× reduction in characterization time, with the prediction error in setup and hold time within 9% of FO4 nominal delay, as compared to that of SPICE simulation results.

Original languageEnglish (US)
Pages (from-to)104-113
Number of pages10
JournalIntegration, the VLSI Journal
Volume49
DOIs
StatePublished - Mar 1 2015

Keywords

  • Compact modeling
  • Design flow
  • Finite-point method
  • Hold time
  • Sequential circuit elements
  • Setup time
  • Timing characterization

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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