FPGA-based high-speed authenticated encryption system

Michael Muehlberghuber, Christoph Keller, Frank K. Gürkaynak, Norbert Felber

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The Advanced Encryption Standard (AES) running in the Galois/Counter Mode of Operation represents a de facto standard in the field of hardware-accelerated, block-cipher-based high-speed authenticated encryption (AE) systems. We propose hardware architectures supporting the Ethernet standard IEEE 802.3ba utilizing different cryptographic primitives suitable for AE applications. Our main design goal was to achieve high throughput on FPGA platforms. Compared to previous works aiming at data rates beyond 100 Gbit/s, our design makes use of an alternative block cipher and an alternative mode of operation, namely Serpent and the offset codebook mode of operation, respectively. Using four cipher cores for the encryption part of the AE architecture, we achieve a throughput of 141 Gbit/s on an Altera Stratix IV FPGA. The design requires 39 kALMs and runs at a maximum clock frequency of 275 MHz. This represents, to the best of our knowledge, the fastest full implementation of an AE scheme on FPGAs to date. In order to make the design applicable in a real-world environment, we developed a custom-designed printed circuit board for the Stratix IV FPGA, suitable to process data with up to 100 Gbit/s.

Original languageEnglish (US)
Title of host publicationVLSI-SoC
Subtitle of host publicationFrom Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Revised Selected Papers
EditorsSrinivas Katkoori, Ricardo Reis, Matthew R. Guthaus, Andreas Burg, Ayse Coskun, Matthew Guthaus, Ricardo Reis, Srinivas Katkoori, Andreas Burg, Ayse Coskun
PublisherSpringer New York LLC
Pages1-20
Number of pages20
ISBN (Print)9783642450723
DOIs
StatePublished - Jan 1 2013
Externally publishedYes
Event20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012 - Santa Cruz, CA, United States
Duration: Oct 7 2012Oct 10 2012

Publication series

NameIFIP Advances in Information and Communication Technology
Volume418
ISSN (Print)1868-4238

Conference

Conference20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012
CountryUnited States
CitySanta Cruz, CA
Period10/7/1210/10/12

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Keywords

  • AES
  • Authenticated encryption
  • FPGA
  • GCM
  • High-throughput architecture
  • OCB
  • Pipelining
  • Serpent

ASJC Scopus subject areas

  • Information Systems
  • Computer Networks and Communications
  • Information Systems and Management

Cite this

Muehlberghuber, M., Keller, C., Gürkaynak, F. K., & Felber, N. (2013). FPGA-based high-speed authenticated encryption system. In S. Katkoori, R. Reis, M. R. Guthaus, A. Burg, A. Coskun, M. Guthaus, R. Reis, S. Katkoori, A. Burg, & A. Coskun (Eds.), VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Revised Selected Papers (pp. 1-20). (IFIP Advances in Information and Communication Technology; Vol. 418). Springer New York LLC. https://doi.org/10.1007/978-3-642-45073-0_1