FPGA based single cycle, reconfigurable router for NoC applications

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

An FPGA based, single cycle, low latency router design that can be reconfigured to 1-D and 2-D network on chip architectures is proposed. The design is highly scalable and exploits the features provided by any standard FPGA platform and can be easily ported to an ASIC or any other FPGA platform. Due to the highly interconnect-centric nature of NoCs, the built-in resources of an FPGA in terms of routing channels and on chip logic are ideal and provide a well-utilized platform for the router design. Experimental results prove the proposed design is robust and cost effective. Each router consumes a mere 2.08 μW per bit per hop of power in the worst case while achieving high clock rates of 325 MHz easily on the target FPGA device post design synthesis and emulation.

Original languageEnglish (US)
Title of host publication2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Pages2428-2431
Number of pages4
DOIs
StatePublished - Sep 9 2013
Event2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
Duration: May 19 2013May 23 2013

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
CountryChina
CityBeijing
Period5/19/135/23/13

Keywords

  • FPGA
  • FSM
  • GALS
  • LUT
  • Network on chip
  • flow control
  • interconnect
  • wormhole router

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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