An FPGA based, single cycle, low latency router design that can be reconfigured to 1-D and 2-D network on chip architectures is proposed. The design is highly scalable and exploits the features provided by any standard FPGA platform and can be easily ported to an ASIC or any other FPGA platform. Due to the highly interconnect-centric nature of NoCs, the built-in resources of an FPGA in terms of routing channels and on chip logic are ideal and provide a well-utilized platform for the router design. Experimental results prove the proposed design is robust and cost effective. Each router consumes a mere 2.08 μW per bit per hop of power in the worst case while achieving high clock rates of 325 MHz easily on the target FPGA device post design synthesis and emulation.