FPGA implementation of advanced FEC schemes for intelligent aggregation networks

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

In state-of-the-art fiber-optics communication systems the fixed forward error correction (FEC) and constellation size are employed. While it is important to closely approach the Shannon limit by using turbo product codes (TPC) and low-density parity-check (LDPC) codes with soft-decision decoding (SDD) algorithm; rate-adaptive techniques, which enable increased information rates over short links and reliable transmission over long links, are likely to become more important with ever-increasing network traffic demands. In this invited paper, we describe a rate adaptive non-binary LDPC coding technique, and demonstrate its flexibility and good performance exhibiting no error floor at BER down to 10-15 in entire code rate range, by FPGA-based emulation, making it a viable solution in the next-generation high-speed intelligent aggregation networks.

Original languageEnglish (US)
Title of host publicationOptical Metro Networks and Short-Haul Systems VIII
PublisherSPIE
Volume9773
ISBN (Electronic)9781510600089
DOIs
StatePublished - 2016
EventOptical Metro Networks and Short-Haul Systems VIII - San Francisco, United States
Duration: Feb 16 2016Feb 18 2016

Other

OtherOptical Metro Networks and Short-Haul Systems VIII
CountryUnited States
CitySan Francisco
Period2/16/162/18/16

Fingerprint

FPGA Implementation
Forward error correction
Error Correction
Fiber optics
Decoding
Field programmable gate arrays (FPGA)
Aggregation
Communication systems
Agglomeration
Fiber Optics Communications
Information Rates
Adaptive Techniques
Low-density Parity-check (LDPC) Codes
Emulation
Network Traffic
Parity
Field Programmable Gate Array
Communication Systems
parity
High Speed

Keywords

  • adaptive coding
  • Fiber-optics communications
  • FPGA implementation
  • intelligent aggregation networks
  • low-density parity-check (LDPC) codes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering

Cite this

Zou, D., & Djordjevic, I. B. (2016). FPGA implementation of advanced FEC schemes for intelligent aggregation networks. In Optical Metro Networks and Short-Haul Systems VIII (Vol. 9773). [977309] SPIE. https://doi.org/10.1117/12.2214884

FPGA implementation of advanced FEC schemes for intelligent aggregation networks. / Zou, Ding; Djordjevic, Ivan B.

Optical Metro Networks and Short-Haul Systems VIII. Vol. 9773 SPIE, 2016. 977309.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zou, D & Djordjevic, IB 2016, FPGA implementation of advanced FEC schemes for intelligent aggregation networks. in Optical Metro Networks and Short-Haul Systems VIII. vol. 9773, 977309, SPIE, Optical Metro Networks and Short-Haul Systems VIII, San Francisco, United States, 2/16/16. https://doi.org/10.1117/12.2214884
Zou D, Djordjevic IB. FPGA implementation of advanced FEC schemes for intelligent aggregation networks. In Optical Metro Networks and Short-Haul Systems VIII. Vol. 9773. SPIE. 2016. 977309 https://doi.org/10.1117/12.2214884
Zou, Ding ; Djordjevic, Ivan B. / FPGA implementation of advanced FEC schemes for intelligent aggregation networks. Optical Metro Networks and Short-Haul Systems VIII. Vol. 9773 SPIE, 2016.
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