Guaranteed error correction of faulty bit-flipping decoders under data-dependent gate failures

Srdan Brkic; Predrag Ivanis; Bane Vasic

doi:10.1109/ISIT.2016.7541561

Guaranteed error correction of faulty bit-flipping decoders under data-dependent gate failures

Srdan Brkic, Predrag Ivanis, Bane Vasic

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

In this paper we analyze the effect of hardware unreliability to performance of bit-flipping decoders of low-density parity-check (LDPC) codes. We apply expander arguments to show that the simple parallel bit flipping decoder, built partially from faulty gates, can correct a linear fraction of worst case channel errors, when gate failures are correlated and dependent on the switching activity of logic gates. In addition, we provide a lower bound on the guaranteed error correction of LDPC codes with left degree of at least eight.

Original language	English (US)
Title of host publication	Proceedings - ISIT 2016; 2016 IEEE International Symposium on Information Theory
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1561-1565
Number of pages	5
ISBN (Electronic)	9781509018062
DOIs	https://doi.org/10.1109/ISIT.2016.7541561
State	Published - Aug 10 2016
Event	2016 IEEE International Symposium on Information Theory, ISIT 2016 - Barcelona, Spain Duration: Jul 10 2016 → Jul 15 2016

Publication series

Name	IEEE International Symposium on Information Theory - Proceedings
Volume	2016-August
ISSN (Print)	2157-8095

Other

Other	2016 IEEE International Symposium on Information Theory, ISIT 2016
Country/Territory	Spain
City	Barcelona
Period	7/10/16 → 7/15/16

ASJC Scopus subject areas

Theoretical Computer Science
Information Systems
Modeling and Simulation
Applied Mathematics

Access to Document

10.1109/ISIT.2016.7541561

Cite this

Brkic, S., Ivanis, P., & Vasic, B. (2016). Guaranteed error correction of faulty bit-flipping decoders under data-dependent gate failures. In Proceedings - ISIT 2016; 2016 IEEE International Symposium on Information Theory (pp. 1561-1565). [7541561] (IEEE International Symposium on Information Theory - Proceedings; Vol. 2016-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISIT.2016.7541561

Guaranteed error correction of faulty bit-flipping decoders under data-dependent gate failures. / Brkic, Srdan; Ivanis, Predrag; Vasic, Bane.

Proceedings - ISIT 2016; 2016 IEEE International Symposium on Information Theory. Institute of Electrical and Electronics Engineers Inc., 2016. p. 1561-1565 7541561 (IEEE International Symposium on Information Theory - Proceedings; Vol. 2016-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Brkic, S, Ivanis, P & Vasic, B 2016, Guaranteed error correction of faulty bit-flipping decoders under data-dependent gate failures. in Proceedings - ISIT 2016; 2016 IEEE International Symposium on Information Theory., 7541561, IEEE International Symposium on Information Theory - Proceedings, vol. 2016-August, Institute of Electrical and Electronics Engineers Inc., pp. 1561-1565, 2016 IEEE International Symposium on Information Theory, ISIT 2016, Barcelona, Spain, 7/10/16. https://doi.org/10.1109/ISIT.2016.7541561

Brkic S, Ivanis P, Vasic B. Guaranteed error correction of faulty bit-flipping decoders under data-dependent gate failures. In Proceedings - ISIT 2016; 2016 IEEE International Symposium on Information Theory. Institute of Electrical and Electronics Engineers Inc. 2016. p. 1561-1565. 7541561. (IEEE International Symposium on Information Theory - Proceedings). https://doi.org/10.1109/ISIT.2016.7541561

Brkic, Srdan ; Ivanis, Predrag ; Vasic, Bane. / Guaranteed error correction of faulty bit-flipping decoders under data-dependent gate failures. Proceedings - ISIT 2016; 2016 IEEE International Symposium on Information Theory. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 1561-1565 (IEEE International Symposium on Information Theory - Proceedings).

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abstract = "In this paper we analyze the effect of hardware unreliability to performance of bit-flipping decoders of low-density parity-check (LDPC) codes. We apply expander arguments to show that the simple parallel bit flipping decoder, built partially from faulty gates, can correct a linear fraction of worst case channel errors, when gate failures are correlated and dependent on the switching activity of logic gates. In addition, we provide a lower bound on the guaranteed error correction of LDPC codes with left degree of at least eight.",

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AB - In this paper we analyze the effect of hardware unreliability to performance of bit-flipping decoders of low-density parity-check (LDPC) codes. We apply expander arguments to show that the simple parallel bit flipping decoder, built partially from faulty gates, can correct a linear fraction of worst case channel errors, when gate failures are correlated and dependent on the switching activity of logic gates. In addition, we provide a lower bound on the guaranteed error correction of LDPC codes with left degree of at least eight.

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Guaranteed error correction of faulty bit-flipping decoders under data-dependent gate failures

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