Guaranteed error correction of faulty bit-flipping decoders under data-dependent gate failures

Srdan Brkic, Predrag Ivanis, Bane V Vasic

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

In this paper we analyze the effect of hardware unreliability to performance of bit-flipping decoders of low-density parity-check (LDPC) codes. We apply expander arguments to show that the simple parallel bit flipping decoder, built partially from faulty gates, can correct a linear fraction of worst case channel errors, when gate failures are correlated and dependent on the switching activity of logic gates. In addition, we provide a lower bound on the guaranteed error correction of LDPC codes with left degree of at least eight.

Original languageEnglish (US)
Title of host publicationProceedings - ISIT 2016; 2016 IEEE International Symposium on Information Theory
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1561-1565
Number of pages5
Volume2016-August
ISBN (Electronic)9781509018062
DOIs
StatePublished - Aug 10 2016
Event2016 IEEE International Symposium on Information Theory, ISIT 2016 - Barcelona, Spain
Duration: Jul 10 2016Jul 15 2016

Other

Other2016 IEEE International Symposium on Information Theory, ISIT 2016
CountrySpain
CityBarcelona
Period7/10/167/15/16

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Information Systems
  • Modeling and Simulation
  • Applied Mathematics

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    Brkic, S., Ivanis, P., & Vasic, B. V. (2016). Guaranteed error correction of faulty bit-flipping decoders under data-dependent gate failures. In Proceedings - ISIT 2016; 2016 IEEE International Symposium on Information Theory (Vol. 2016-August, pp. 1561-1565). [7541561] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISIT.2016.7541561