Abstract
In this paper we analyze the effect of hardware unreliability to performance of bit-flipping decoders of low-density parity-check (LDPC) codes. We apply expander arguments to show that the simple parallel bit flipping decoder, built partially from faulty gates, can correct a linear fraction of worst case channel errors, when gate failures are correlated and dependent on the switching activity of logic gates. In addition, we provide a lower bound on the guaranteed error correction of LDPC codes with left degree of at least eight.
Original language | English (US) |
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Title of host publication | Proceedings - ISIT 2016; 2016 IEEE International Symposium on Information Theory |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 1561-1565 |
Number of pages | 5 |
Volume | 2016-August |
ISBN (Electronic) | 9781509018062 |
DOIs | |
State | Published - Aug 10 2016 |
Event | 2016 IEEE International Symposium on Information Theory, ISIT 2016 - Barcelona, Spain Duration: Jul 10 2016 → Jul 15 2016 |
Other
Other | 2016 IEEE International Symposium on Information Theory, ISIT 2016 |
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Country | Spain |
City | Barcelona |
Period | 7/10/16 → 7/15/16 |
ASJC Scopus subject areas
- Theoretical Computer Science
- Information Systems
- Modeling and Simulation
- Applied Mathematics