Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders

Khoa Le; Fakhreddine Ghaffari; David Declercq; Bane V Vasic

doi:10.1109/ISCAS.2017.8050695

Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders

Khoa Le, Fakhreddine Ghaffari, David Declercq, Bane V Vasic

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

The Probabilistic Gradient Descent Bit-Flipping (PGDBF) decoder has been proposed as a very promising hard-decision Low-Density Parity-Check (LDPC) decoder with a large gain in error correction. However, this impressive decoding gain is reported to come along with a non-negligible extra complexity due to the additional Perturbation Block (PB) required on top of the Gradient Descent Bit-Flipping (GDBF) decoder. In this paper, an efficient solution to implement this PB is introduced which is shown to keep the decoding gain as good as the theoretical PGDBF decoder while requiring a very small hardware overhead compared to the non-probabilistic GDBF. The proposed architecture is designed basing on a statistical analysis conducted to find the key features of the randomness needed to maintain the decoding gain and to reveal the simplification directions. The efficiency of our proposed method is confirmed by the synthesis results of decoder implementations on ASIC with 65nm CMOS technology and performance simulations.

Original language	English (US)
Title of host publication	IEEE International Symposium on Circuits and Systems
Subtitle of host publication	From Dreams to Innovation, ISCAS 2017 - Conference Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467368520
DOIs	https://doi.org/10.1109/ISCAS.2017.8050695
State	Published - Sep 25 2017
Event	50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States Duration: May 28 2017 → May 31 2017

Other

Other	50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Country	United States
City	Baltimore
Period	5/28/17 → 5/31/17

Keywords

Bit-Flipping decoder
low-complexity implementation
Low-Density Parity-Check
random generator

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2017.8050695

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Le, K., Ghaffari, F., Declercq, D., & Vasic, B. V. (2017). Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings [8050695] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2017.8050695

Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders. / Le, Khoa; Ghaffari, Fakhreddine; Declercq, David; Vasic, Bane V.

IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. 8050695.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Le, K, Ghaffari, F, Declercq, D & Vasic, BV 2017, Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders. in IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings., 8050695, Institute of Electrical and Electronics Engineers Inc., 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, United States, 5/28/17. https://doi.org/10.1109/ISCAS.2017.8050695

Le K, Ghaffari F, Declercq D, Vasic BV. Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. 8050695 https://doi.org/10.1109/ISCAS.2017.8050695

@inproceedings{e0cc446a85d74fbdb121dd00694e6249,

title = "Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders",

abstract = "The Probabilistic Gradient Descent Bit-Flipping (PGDBF) decoder has been proposed as a very promising hard-decision Low-Density Parity-Check (LDPC) decoder with a large gain in error correction. However, this impressive decoding gain is reported to come along with a non-negligible extra complexity due to the additional Perturbation Block (PB) required on top of the Gradient Descent Bit-Flipping (GDBF) decoder. In this paper, an efficient solution to implement this PB is introduced which is shown to keep the decoding gain as good as the theoretical PGDBF decoder while requiring a very small hardware overhead compared to the non-probabilistic GDBF. The proposed architecture is designed basing on a statistical analysis conducted to find the key features of the randomness needed to maintain the decoding gain and to reveal the simplification directions. The efficiency of our proposed method is confirmed by the synthesis results of decoder implementations on ASIC with 65nm CMOS technology and performance simulations.",

keywords = "Bit-Flipping decoder, low-complexity implementation, Low-Density Parity-Check, random generator",

author = "Khoa Le and Fakhreddine Ghaffari and David Declercq and Vasic, {Bane V}",

year = "2017",

month = sep,

day = "25",

doi = "10.1109/ISCAS.2017.8050695",

language = "English (US)",

booktitle = "IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 ; Conference date: 28-05-2017 Through 31-05-2017",

}

TY - GEN

T1 - Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders

AU - Le, Khoa

AU - Ghaffari, Fakhreddine

AU - Declercq, David

AU - Vasic, Bane V

PY - 2017/9/25

Y1 - 2017/9/25

N2 - The Probabilistic Gradient Descent Bit-Flipping (PGDBF) decoder has been proposed as a very promising hard-decision Low-Density Parity-Check (LDPC) decoder with a large gain in error correction. However, this impressive decoding gain is reported to come along with a non-negligible extra complexity due to the additional Perturbation Block (PB) required on top of the Gradient Descent Bit-Flipping (GDBF) decoder. In this paper, an efficient solution to implement this PB is introduced which is shown to keep the decoding gain as good as the theoretical PGDBF decoder while requiring a very small hardware overhead compared to the non-probabilistic GDBF. The proposed architecture is designed basing on a statistical analysis conducted to find the key features of the randomness needed to maintain the decoding gain and to reveal the simplification directions. The efficiency of our proposed method is confirmed by the synthesis results of decoder implementations on ASIC with 65nm CMOS technology and performance simulations.

AB - The Probabilistic Gradient Descent Bit-Flipping (PGDBF) decoder has been proposed as a very promising hard-decision Low-Density Parity-Check (LDPC) decoder with a large gain in error correction. However, this impressive decoding gain is reported to come along with a non-negligible extra complexity due to the additional Perturbation Block (PB) required on top of the Gradient Descent Bit-Flipping (GDBF) decoder. In this paper, an efficient solution to implement this PB is introduced which is shown to keep the decoding gain as good as the theoretical PGDBF decoder while requiring a very small hardware overhead compared to the non-probabilistic GDBF. The proposed architecture is designed basing on a statistical analysis conducted to find the key features of the randomness needed to maintain the decoding gain and to reveal the simplification directions. The efficiency of our proposed method is confirmed by the synthesis results of decoder implementations on ASIC with 65nm CMOS technology and performance simulations.

KW - Bit-Flipping decoder

KW - low-complexity implementation

KW - Low-Density Parity-Check

KW - random generator

UR - http://www.scopus.com/inward/record.url?scp=85032676162&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85032676162&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2017.8050695

DO - 10.1109/ISCAS.2017.8050695

M3 - Conference contribution

AN - SCOPUS:85032676162

BT - IEEE International Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017

Y2 - 28 May 2017 through 31 May 2017

ER -