Abstract
The Probabilistic Gradient Descent Bit-Flipping (PGDBF) decoder has been proposed as a very promising hard-decision Low-Density Parity-Check (LDPC) decoder with a large gain in error correction. However, this impressive decoding gain is reported to come along with a non-negligible extra complexity due to the additional Perturbation Block (PB) required on top of the Gradient Descent Bit-Flipping (GDBF) decoder. In this paper, an efficient solution to implement this PB is introduced which is shown to keep the decoding gain as good as the theoretical PGDBF decoder while requiring a very small hardware overhead compared to the non-probabilistic GDBF. The proposed architecture is designed basing on a statistical analysis conducted to find the key features of the randomness needed to maintain the decoding gain and to reveal the simplification directions. The efficiency of our proposed method is confirmed by the synthesis results of decoder implementations on ASIC with 65nm CMOS technology and performance simulations.
Original language | English (US) |
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Title of host publication | IEEE International Symposium on Circuits and Systems |
Subtitle of host publication | From Dreams to Innovation, ISCAS 2017 - Conference Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781467368520 |
DOIs | |
State | Published - Sep 25 2017 |
Event | 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States Duration: May 28 2017 → May 31 2017 |
Other
Other | 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 |
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Country | United States |
City | Baltimore |
Period | 5/28/17 → 5/31/17 |
Keywords
- Bit-Flipping decoder
- low-complexity implementation
- Low-Density Parity-Check
- random generator
ASJC Scopus subject areas
- Electrical and Electronic Engineering