TY - GEN
T1 - Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders
AU - Le, Khoa
AU - Ghaffari, Fakhreddine
AU - Declercq, David
AU - Vasic, Bane
N1 - Funding Information:
ACKNOWLEDGMENT This work was funded in parts by the Seventh Framework Programme of the European Union, under Grant Agreement number 309129 (i-RISC project), the Franco-Romanian (ANR-UEFISCDI) Joint Research Program (DIAMOND project), and by the NSF under grants CCF-0963726, CCF-1314147 and ECCS-1500170. Bane Vasić acknowledges the support of the Fulbright Scholar Program.
PY - 2017/9/25
Y1 - 2017/9/25
N2 - The Probabilistic Gradient Descent Bit-Flipping (PGDBF) decoder has been proposed as a very promising hard-decision Low-Density Parity-Check (LDPC) decoder with a large gain in error correction. However, this impressive decoding gain is reported to come along with a non-negligible extra complexity due to the additional Perturbation Block (PB) required on top of the Gradient Descent Bit-Flipping (GDBF) decoder. In this paper, an efficient solution to implement this PB is introduced which is shown to keep the decoding gain as good as the theoretical PGDBF decoder while requiring a very small hardware overhead compared to the non-probabilistic GDBF. The proposed architecture is designed basing on a statistical analysis conducted to find the key features of the randomness needed to maintain the decoding gain and to reveal the simplification directions. The efficiency of our proposed method is confirmed by the synthesis results of decoder implementations on ASIC with 65nm CMOS technology and performance simulations.
AB - The Probabilistic Gradient Descent Bit-Flipping (PGDBF) decoder has been proposed as a very promising hard-decision Low-Density Parity-Check (LDPC) decoder with a large gain in error correction. However, this impressive decoding gain is reported to come along with a non-negligible extra complexity due to the additional Perturbation Block (PB) required on top of the Gradient Descent Bit-Flipping (GDBF) decoder. In this paper, an efficient solution to implement this PB is introduced which is shown to keep the decoding gain as good as the theoretical PGDBF decoder while requiring a very small hardware overhead compared to the non-probabilistic GDBF. The proposed architecture is designed basing on a statistical analysis conducted to find the key features of the randomness needed to maintain the decoding gain and to reveal the simplification directions. The efficiency of our proposed method is confirmed by the synthesis results of decoder implementations on ASIC with 65nm CMOS technology and performance simulations.
KW - Bit-Flipping decoder
KW - Low-Density Parity-Check
KW - low-complexity implementation
KW - random generator
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U2 - 10.1109/ISCAS.2017.8050695
DO - 10.1109/ISCAS.2017.8050695
M3 - Conference contribution
AN - SCOPUS:85032676162
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Y2 - 28 May 2017 through 31 May 2017
ER -