High performance sub-100 nm Si thin-film transistors by Pattern-controlled crystallization of Thin channel layer and High temperature annealing

Jian Gu, Wei Wu, S. Y. Chou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this work, we report the fabrication of high performance thin-film transistors (TFTs) down to sub-100 nm regime using Pattern-controlled crystallization of Thin channel layer and High temperature annealing (PaTH). High temperature is used to improve the film quality. Thin body thickness (Tsi) is used to suppress the short channel effects. The devices showed superior switching properties and device-to-device uniformity over conventional poly-Si TFTs.

Original languageEnglish (US)
Title of host publicationDevice Research Conference - Conference Digest, DRC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages49-50
Number of pages2
Volume2002-January
ISBN (Print)0780373170
DOIs
Publication statusPublished - 2002
Externally publishedYes
Event60th Device Research Conference, DRC 2002 - Santa Barbara, United States
Duration: Jun 24 2002Jun 26 2002

Other

Other60th Device Research Conference, DRC 2002
CountryUnited States
CitySanta Barbara
Period6/24/026/26/02

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Keywords

  • Annealing
  • Crystallization
  • Fabrication
  • Grain boundaries
  • Immune system
  • Laboratories
  • Silicon on insulator technology
  • Statistics
  • Temperature
  • Thin film transistors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Gu, J., Wu, W., & Chou, S. Y. (2002). High performance sub-100 nm Si thin-film transistors by Pattern-controlled crystallization of Thin channel layer and High temperature annealing. In Device Research Conference - Conference Digest, DRC (Vol. 2002-January, pp. 49-50). [1029501] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DRC.2002.1029501