There is increasing demand for fast floating-point arithmetic support to make Field Programmable Gate Arrays (FPGAs) a practical option for scientific computing applications. In existing FPGA based double-precision floating-point division approaches, operational frequency of the design is bounded by the performance of mantissa stage. In earlier work we introduced a new algorithm for mantissa multiplication to implement IEEE-754 compliant multiplier. In this paper we apply the same algorithm onto division by convergence technique to implement the division operation. Division algorithm reaches a maximum of 256MHz operational frequency on Virtex-4 platform which outperforms algorithm and IP-Core based solutions in the academia as well as Xilinx LogiCORE solutions when no embedded resources are used. Operational frequency is improved by 153%, 48% and 20% compared to algorithm and IP core based solutions of academia and Xilinx LogiCORE solutions respectively. Area overhead is larger then IP-Core based solutions, but we rely on the capacity trend of contemporary FPGAs.