Highly parallel FPGA based IEEE-754 compliant double-precision floating-point division

Sandeep Venishetti, Ali Akoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

There is increasing demand for fast floating-point arithmetic support to make Field Programmable Gate Arrays (FPGAs) a practical option for scientific computing applications. In existing FPGA based double-precision floating-point division approaches, operational frequency of the design is bounded by the performance of mantissa stage. In earlier work we introduced a new algorithm for mantissa multiplication to implement IEEE-754 compliant multiplier. In this paper we apply the same algorithm onto division by convergence technique to implement the division operation. Division algorithm reaches a maximum of 256MHz operational frequency on Virtex-4 platform which outperforms algorithm and IP-Core based solutions in the academia as well as Xilinx LogiCORE solutions when no embedded resources are used. Operational frequency is improved by 153%, 48% and 20% compared to algorithm and IP core based solutions of academia and Xilinx LogiCORE solutions respectively. Area overhead is larger then IP-Core based solutions, but we rely on the capacity trend of contemporary FPGAs.

Original languageEnglish (US)
Title of host publicationProceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
Pages159-165
Number of pages7
StatePublished - 2008
Event2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008 - Las Vegas, NV, United States
Duration: Jul 14 2008Jul 17 2008

Other

Other2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
CountryUnited States
CityLas Vegas, NV
Period7/14/087/17/08

Fingerprint

Field programmable gate arrays (FPGA)
Digital arithmetic
Natural sciences computing
Intellectual property core

Keywords

  • Division
  • Floating point arithmetic
  • FPGA

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture
  • Software

Cite this

Venishetti, S., & Akoglu, A. (2008). Highly parallel FPGA based IEEE-754 compliant double-precision floating-point division. In Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008 (pp. 159-165)

Highly parallel FPGA based IEEE-754 compliant double-precision floating-point division. / Venishetti, Sandeep; Akoglu, Ali.

Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. 2008. p. 159-165.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Venishetti, S & Akoglu, A 2008, Highly parallel FPGA based IEEE-754 compliant double-precision floating-point division. in Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. pp. 159-165, 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008, Las Vegas, NV, United States, 7/14/08.
Venishetti S, Akoglu A. Highly parallel FPGA based IEEE-754 compliant double-precision floating-point division. In Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. 2008. p. 159-165
Venishetti, Sandeep ; Akoglu, Ali. / Highly parallel FPGA based IEEE-754 compliant double-precision floating-point division. Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. 2008. pp. 159-165
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