In recent years, three-dimensional GaN-based transistors have been intensively studied for their dramatically improved output power, better gate controllability, and shorter channels for speedup and miniaturization. However, thermal analysis of such devices is often oversimplified using the conventional Fourier's law and bulk material properties in thermal simulations. In this aspect, accurate temperature predictions can be achieved by coupled phonon and electron Monte Carlo simulations that track the movement and scattering of individual phonons and electrons. However, the heavy computational load often restricts such simulations to nanoscale devices, while a real chip is of millimeter to centimeter sizes. This issue can be addressed by a hybrid simulation technique that employs the Fourier's law for regions away from the hot spot. Using this technique, accurate electrothermal simulations are carried out on a nanowire-based GaN transistor to reveal the temperature rise in such devices.
|Original language||English (US)|
|State||Published - Jul 27 2017|
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