iDEAL: Inter-router dual-function energy and area-efficient links for Network-on-Chip (NoC) architectures

Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

47 Citations (Scopus)

Abstract

Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the deep sub-micron regime. However, the shrinking feature size limits the performance of NoCs due to power and area constraints. Research into the optimization of NoCs has shown that a reduction in the number of buffers in the NoC routers reduces the power and area overhead but degrades the network performance. In this paper, we propose iDEAL, a low-power area-efflcient NoC architecture by reducing the number of buffers within the router. To overcome the performance degradation caused by the reduced buffer size, we propose to use adaptive dual-function links capable of data transmission as well as data storage when required. Simulation results for the proposed architecture show that reducing the router buffer size in half and using the adaptive dual-function links achieves nearly 40% savings in buffer power, 30% savings in overall network power and about 41% savings in the router area, with only a marginal 1-3% drop in performance. Moreover, the performance in iDEAL can be further improved by aggressive and speculative flow control techniques.

Original languageEnglish (US)
Title of host publicationProceedings - International Symposium on Computer Architecture
Pages241-250
Number of pages10
DOIs
StatePublished - 2008
EventISCA 2008, 35th International Symposium on Computer Architecture - Beijing, China
Duration: Jun 21 2008Jun 25 2008

Other

OtherISCA 2008, 35th International Symposium on Computer Architecture
CountryChina
CityBeijing
Period6/21/086/25/08

Fingerprint

Routers
Network performance
Flow control
Data communication systems
Telecommunication links
Wire
Data storage equipment
Degradation
Network-on-chip

Keywords

  • Interconnects
  • Low-power architecture
  • Network-on-chip

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Kodi, A. K., Sarathy, A., & Louri, A. (2008). iDEAL: Inter-router dual-function energy and area-efficient links for Network-on-Chip (NoC) architectures. In Proceedings - International Symposium on Computer Architecture (pp. 241-250). [4556730] https://doi.org/10.1109/ISCA.2008.14

iDEAL : Inter-router dual-function energy and area-efficient links for Network-on-Chip (NoC) architectures. / Kodi, Avinash Karanth; Sarathy, Ashwini; Louri, Ahmed.

Proceedings - International Symposium on Computer Architecture. 2008. p. 241-250 4556730.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kodi, AK, Sarathy, A & Louri, A 2008, iDEAL: Inter-router dual-function energy and area-efficient links for Network-on-Chip (NoC) architectures. in Proceedings - International Symposium on Computer Architecture., 4556730, pp. 241-250, ISCA 2008, 35th International Symposium on Computer Architecture, Beijing, China, 6/21/08. https://doi.org/10.1109/ISCA.2008.14
Kodi AK, Sarathy A, Louri A. iDEAL: Inter-router dual-function energy and area-efficient links for Network-on-Chip (NoC) architectures. In Proceedings - International Symposium on Computer Architecture. 2008. p. 241-250. 4556730 https://doi.org/10.1109/ISCA.2008.14
Kodi, Avinash Karanth ; Sarathy, Ashwini ; Louri, Ahmed. / iDEAL : Inter-router dual-function energy and area-efficient links for Network-on-Chip (NoC) architectures. Proceedings - International Symposium on Computer Architecture. 2008. pp. 241-250
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