Information theoretic modeling and analysis for global interconnects with process variations

Stojan Z. Denic, Bane Vasic, Charalambos D. Charalambous, Jifeng Chen, Janet M. Wang

Research output: Contribution to journalArticle

3 Scopus citations

Abstract

As the CMOS semiconductor technology enters nanometer regime, interconnect processes must be compatible with device roadmaps and meet manufacturing targets at the specified wafer size. The resulting ubiquitous process variations cause errors in data delivering through interconnects. This paper proposes an Information Theory based design method to accommodate process variations. Different from the traditional delay based design metric, the current approach uses achievable rate to relate interconnect designs directly to communication applications. More specifically, the data communication over a typical interconnect, a bus, subject to process variations (uncertain bus), is defined as a communication problem under uncertainty. A data rate, called the achievable rate, is computed for such a bus, which represents the lower bound on the maximal data rate attainable over the bus. When a data rate applied over the bus is smaller than the achievable data rate, a reliable communication can be guaranteed regardless of process variations, i.e., a bit error rate arbitrarily close to zero is achievable. A single communication strategy to combat the process variations is proposed whose code rate is equal to the computed achievable rate. The simulations show that the variations in the interconnect resistivity could have the most harmful effect regarding the achievable rate reduction. Also, the simulations illustrate the importance of taking into account bus parasitic parameters correlations when measuring the influence of the process variations on the achievable rates.

Original languageEnglish (US)
Article number5352230
Pages (from-to)397-410
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume19
Issue number3
DOIs
StatePublished - Mar 2011

Keywords

  • Achievable rate
  • bit error rate process variations
  • global interconnect
  • information theory

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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