Three independent topics which illustrate innovative methods for improving testability are described. First, a technique which utilizes a card logic tester as a vehicle for evaluating the effectiveness of new chip-level tests is described. This technique allows rapid implementation and verification of various test algorithms as chip failure mechanisms are discovered. Second, a methodology which combines simulation data with the capabilities of a tester language to provide early verification of the AC characteristics of components is presented. Third and finally, the authors consider tester language limitations and how adjustments can be made to component timing specifications to overcome these restrictions. These techniques were successfully implemented using Programming Language for Testing (PLT). With these methods, the testability and hence the quality of recent IBM products were improved in a cost-effective manner.