Insertion loss characterization of tightly spaced interconnects with an embedded patterned layer

Marcos A. Vargas, Kathleen L Melde

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

As smaller packaging footprints and faster data rates are pursued, signal integrity suffers as a result of interconnects routed in close proximity to one another. This paper focuses on two tightly spaced microstrips and highlights the use of an embedded patterned layer (EPL) of conductive elements to improve insertion loss and far end crosstalk. The frequency domain S-parameter performance is characterized with a commercial full wave solver and effective permittivity is extracted. The effect of relative permittivity on insertion loss is investigated. The largest improvement is seen for the permittivity of 10, with insertion loss improving from -6.3dB to -2.3dB at 67GHz. The same case shows a far end crosstalk improvement from -1.5dB to -4.8dB at 67GHz. However, a tradeoff with return loss and near end crosstalk is observed.

Original languageEnglish (US)
Title of host publication2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013
PublisherIEEE Computer Society
Pages21-24
Number of pages4
ISBN (Print)9781467325363
DOIs
StatePublished - 2013
Event2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013 - San Jose, CA, United States
Duration: Oct 27 2013Oct 30 2013

Other

Other2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013
CountryUnited States
CitySan Jose, CA
Period10/27/1310/30/13

Fingerprint

Crosstalk
Insertion losses
Permittivity
Scattering parameters
Packaging

Keywords

  • Crosstalk
  • insertion loss
  • interconnects
  • metasurface
  • microstrip

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Vargas, M. A., & Melde, K. L. (2013). Insertion loss characterization of tightly spaced interconnects with an embedded patterned layer. In 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013 (pp. 21-24). [6703458] IEEE Computer Society. https://doi.org/10.1109/EPEPS.2013.6703458

Insertion loss characterization of tightly spaced interconnects with an embedded patterned layer. / Vargas, Marcos A.; Melde, Kathleen L.

2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013. IEEE Computer Society, 2013. p. 21-24 6703458.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Vargas, MA & Melde, KL 2013, Insertion loss characterization of tightly spaced interconnects with an embedded patterned layer. in 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013., 6703458, IEEE Computer Society, pp. 21-24, 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013, San Jose, CA, United States, 10/27/13. https://doi.org/10.1109/EPEPS.2013.6703458
Vargas MA, Melde KL. Insertion loss characterization of tightly spaced interconnects with an embedded patterned layer. In 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013. IEEE Computer Society. 2013. p. 21-24. 6703458 https://doi.org/10.1109/EPEPS.2013.6703458
Vargas, Marcos A. ; Melde, Kathleen L. / Insertion loss characterization of tightly spaced interconnects with an embedded patterned layer. 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013. IEEE Computer Society, 2013. pp. 21-24
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