The role of packaging in semiconductor electronic applications is to protect and preserve the performance of the semiconductor device from electrical, hygro-thermo-mechanical, and chemical corruption or impairment. This role has become more and more important as well as difﬁcult to execute as device performance, complexity, and functionality increase with each succeeding generation of technology. These generations are succinctly captured in the 2005 International Technology Roadmap for Semiconductors (ITRS) , published by the Semiconductor Industry Association, and they have been highlighted in the Overall Roadmap Technology Characteristics section of the ITRS. The present article will not focus on many types of packaging that have been developed in the past or seek to give a fundamental treatment of the complex phenomena that occur in the conventional package during use. These topics have been covered in a comprehensive manner in other sources [2,3]. Instead, the authors will try to acquaint the semiconductor engineer with the areas of fundamental importance in packaging; as it evolves from present practices into the future and provide some overview of current modeling and analysis methods being used by package design engineers.
|Original language||English (US)|
|Title of host publication||Handbook of Semiconductor Manufacturing Technology, Second Edition|
|ISBN (Print)||1574446754, 9781574446753|
|State||Published - Jan 1 2007|
ASJC Scopus subject areas