Integration of net-length factor with timing- and routability-riven clustering algorithms

Hanyu Liu, Senthilkumar T. Rajavel, Ali Akoglu

Research output: Contribution to journalArticle

Abstract

In FPGA CAD flow, the clustering stage builds the foundation for placement and routing stages and affects performance parameters, such as routability, delay, and channel width significantly. Net sharing and criticality are the two most commonly used factors in clustering cost functions. With this study, we first derive third term net-length factor and then design a generic method for integrating net length into the clustering algorithms. Net-length factor enables characterizing the nets based on the routing stress they might cause during later stages of the CAD flow and is essential for enhancing the routability of the design. We evaluate the effectiveness of integrating net length as a factor into the well-known timing (T-VPack)- depopulation (T-NDPack)- and routability (iRAC and T-RPack)-driven clustering algorithms. Through exhaustive experimental studies we show that net-length factor consistently helps improve the channel-width performance of routability- depopulation- and timing-driven clustering algorithms that do not explicitly target low fan-out nets in their cost functions. Particularly net-length factor leads to average reduction in channel width for T-VPack T-RPack and T-NDPack by 11.6% 10.8% and 14.2% respectively and in a majority of the cases improves the critical-path delay without increasing the array size. Categories and Subject Descriptors: B.7.1 [Integrated Circuits]: Types and Design Styles-Gate arrays General Terms: Design Performance.

Original languageEnglish (US)
Article number12
JournalACM Transactions on Reconfigurable Technology and Systems
Volume6
Issue number3
DOIs
StatePublished - Oct 2013

Fingerprint

Clustering algorithms
Cost functions
Computer aided design
Fans
Integrated circuits
Field programmable gate arrays (FPGA)

Keywords

  • Channel width
  • Clustering
  • Field programmable gate array
  • Net length prediction

ASJC Scopus subject areas

  • Computer Science(all)

Cite this

Integration of net-length factor with timing- and routability-riven clustering algorithms. / Liu, Hanyu; Rajavel, Senthilkumar T.; Akoglu, Ali.

In: ACM Transactions on Reconfigurable Technology and Systems, Vol. 6, No. 3, 12, 10.2013.

Research output: Contribution to journalArticle

@article{801f5c104be34bd39b5b5ca60657b787,
title = "Integration of net-length factor with timing- and routability-riven clustering algorithms",
abstract = "In FPGA CAD flow, the clustering stage builds the foundation for placement and routing stages and affects performance parameters, such as routability, delay, and channel width significantly. Net sharing and criticality are the two most commonly used factors in clustering cost functions. With this study, we first derive third term net-length factor and then design a generic method for integrating net length into the clustering algorithms. Net-length factor enables characterizing the nets based on the routing stress they might cause during later stages of the CAD flow and is essential for enhancing the routability of the design. We evaluate the effectiveness of integrating net length as a factor into the well-known timing (T-VPack)- depopulation (T-NDPack)- and routability (iRAC and T-RPack)-driven clustering algorithms. Through exhaustive experimental studies we show that net-length factor consistently helps improve the channel-width performance of routability- depopulation- and timing-driven clustering algorithms that do not explicitly target low fan-out nets in their cost functions. Particularly net-length factor leads to average reduction in channel width for T-VPack T-RPack and T-NDPack by 11.6{\%} 10.8{\%} and 14.2{\%} respectively and in a majority of the cases improves the critical-path delay without increasing the array size. Categories and Subject Descriptors: B.7.1 [Integrated Circuits]: Types and Design Styles-Gate arrays General Terms: Design Performance.",
keywords = "Channel width, Clustering, Field programmable gate array, Net length prediction",
author = "Hanyu Liu and Rajavel, {Senthilkumar T.} and Ali Akoglu",
year = "2013",
month = "10",
doi = "10.1145/2517324",
language = "English (US)",
volume = "6",
journal = "ACM Transactions on Reconfigurable Technology and Systems",
issn = "1936-7406",
publisher = "Association for Computing Machinery (ACM)",
number = "3",

}

TY - JOUR

T1 - Integration of net-length factor with timing- and routability-riven clustering algorithms

AU - Liu, Hanyu

AU - Rajavel, Senthilkumar T.

AU - Akoglu, Ali

PY - 2013/10

Y1 - 2013/10

N2 - In FPGA CAD flow, the clustering stage builds the foundation for placement and routing stages and affects performance parameters, such as routability, delay, and channel width significantly. Net sharing and criticality are the two most commonly used factors in clustering cost functions. With this study, we first derive third term net-length factor and then design a generic method for integrating net length into the clustering algorithms. Net-length factor enables characterizing the nets based on the routing stress they might cause during later stages of the CAD flow and is essential for enhancing the routability of the design. We evaluate the effectiveness of integrating net length as a factor into the well-known timing (T-VPack)- depopulation (T-NDPack)- and routability (iRAC and T-RPack)-driven clustering algorithms. Through exhaustive experimental studies we show that net-length factor consistently helps improve the channel-width performance of routability- depopulation- and timing-driven clustering algorithms that do not explicitly target low fan-out nets in their cost functions. Particularly net-length factor leads to average reduction in channel width for T-VPack T-RPack and T-NDPack by 11.6% 10.8% and 14.2% respectively and in a majority of the cases improves the critical-path delay without increasing the array size. Categories and Subject Descriptors: B.7.1 [Integrated Circuits]: Types and Design Styles-Gate arrays General Terms: Design Performance.

AB - In FPGA CAD flow, the clustering stage builds the foundation for placement and routing stages and affects performance parameters, such as routability, delay, and channel width significantly. Net sharing and criticality are the two most commonly used factors in clustering cost functions. With this study, we first derive third term net-length factor and then design a generic method for integrating net length into the clustering algorithms. Net-length factor enables characterizing the nets based on the routing stress they might cause during later stages of the CAD flow and is essential for enhancing the routability of the design. We evaluate the effectiveness of integrating net length as a factor into the well-known timing (T-VPack)- depopulation (T-NDPack)- and routability (iRAC and T-RPack)-driven clustering algorithms. Through exhaustive experimental studies we show that net-length factor consistently helps improve the channel-width performance of routability- depopulation- and timing-driven clustering algorithms that do not explicitly target low fan-out nets in their cost functions. Particularly net-length factor leads to average reduction in channel width for T-VPack T-RPack and T-NDPack by 11.6% 10.8% and 14.2% respectively and in a majority of the cases improves the critical-path delay without increasing the array size. Categories and Subject Descriptors: B.7.1 [Integrated Circuits]: Types and Design Styles-Gate arrays General Terms: Design Performance.

KW - Channel width

KW - Clustering

KW - Field programmable gate array

KW - Net length prediction

UR - http://www.scopus.com/inward/record.url?scp=84886031563&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84886031563&partnerID=8YFLogxK

U2 - 10.1145/2517324

DO - 10.1145/2517324

M3 - Article

VL - 6

JO - ACM Transactions on Reconfigurable Technology and Systems

JF - ACM Transactions on Reconfigurable Technology and Systems

SN - 1936-7406

IS - 3

M1 - 12

ER -