Abstract
As technology scales, Network-on-Chips (NoCs), currently being used for on-chip communication in manycore architectures, face several problems including high network latency, excessive power consumption, and low reliability. Simultaneously addressing these problems is proving to be difficult due to the explosion of the design space and the complexity of handling many trade-offs. In this paper, we propose IntelliNoC, an intelligent NoC design framework which introduces architectural innovations and uses reinforcement learning to manage the design complexity and simultaneously optimize performance, energy-efficiency, and reliability in a holistic manner. IntelliNoC integrates three NoC architectural techniques: (1) multifunction adaptive channels (MFACs) to improve energy-efficiency; (2) adaptive error detection/correction and re-transmission control to enhance reliability; and (3) a stress-relaxing bypass feature which dynamically powers off NoC components to prevent overheating and fatigue. To handle the complex dynamic interactions induced by these techniques, we train a dynamic control policy using Q-learning, with the goal of providing improved fault-tolerance and performance while reducing power consumption and area overhead. Simulation using PARSEC benchmarks shows that our proposed IntelliNoC design improves energy-efficiency by 67% and mean-time-to-failure (MTTF) by 77%, and decreases end-to-end packet latency by 32% and area requirements by 25% over baseline NoC architecture.
| Original language | English (US) |
|---|---|
| Title of host publication | ISCA 2019 - Proceedings of the 2019 46th International Symposium on Computer Architecture |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 589-600 |
| Number of pages | 12 |
| ISBN (Electronic) | 9781450366694 |
| DOIs | |
| State | Published - Jun 22 2019 |
| Event | 46th International Symposium on Computer Architecture, ISCA 2019 - Phoenix, United States Duration: Jun 22 2019 → Jun 26 2019 |
Publication series
| Name | Proceedings - International Symposium on Computer Architecture |
|---|---|
| ISSN (Print) | 1063-6897 |
Conference
| Conference | 46th International Symposium on Computer Architecture, ISCA 2019 |
|---|---|
| Country | United States |
| City | Phoenix |
| Period | 6/22/19 → 6/26/19 |
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Keywords
- Energy-efficiency
- Network-on-chip (NoC)
- NoC performance
- Reinforcement learning
- Reliability
ASJC Scopus subject areas
- Hardware and Architecture
Cite this
IntelliNoC : A holistic design framework for energy-efficient and reliable on-chip communication for manycores. / Wang, Ke; Louri, Ahmed; Karanth, Avinash; Bunescu, Razvan.
ISCA 2019 - Proceedings of the 2019 46th International Symposium on Computer Architecture. Institute of Electrical and Electronics Engineers Inc., 2019. p. 589-600 (Proceedings - International Symposium on Computer Architecture).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - IntelliNoC
T2 - A holistic design framework for energy-efficient and reliable on-chip communication for manycores
AU - Wang, Ke
AU - Louri, Ahmed
AU - Karanth, Avinash
AU - Bunescu, Razvan
PY - 2019/6/22
Y1 - 2019/6/22
N2 - As technology scales, Network-on-Chips (NoCs), currently being used for on-chip communication in manycore architectures, face several problems including high network latency, excessive power consumption, and low reliability. Simultaneously addressing these problems is proving to be difficult due to the explosion of the design space and the complexity of handling many trade-offs. In this paper, we propose IntelliNoC, an intelligent NoC design framework which introduces architectural innovations and uses reinforcement learning to manage the design complexity and simultaneously optimize performance, energy-efficiency, and reliability in a holistic manner. IntelliNoC integrates three NoC architectural techniques: (1) multifunction adaptive channels (MFACs) to improve energy-efficiency; (2) adaptive error detection/correction and re-transmission control to enhance reliability; and (3) a stress-relaxing bypass feature which dynamically powers off NoC components to prevent overheating and fatigue. To handle the complex dynamic interactions induced by these techniques, we train a dynamic control policy using Q-learning, with the goal of providing improved fault-tolerance and performance while reducing power consumption and area overhead. Simulation using PARSEC benchmarks shows that our proposed IntelliNoC design improves energy-efficiency by 67% and mean-time-to-failure (MTTF) by 77%, and decreases end-to-end packet latency by 32% and area requirements by 25% over baseline NoC architecture.
AB - As technology scales, Network-on-Chips (NoCs), currently being used for on-chip communication in manycore architectures, face several problems including high network latency, excessive power consumption, and low reliability. Simultaneously addressing these problems is proving to be difficult due to the explosion of the design space and the complexity of handling many trade-offs. In this paper, we propose IntelliNoC, an intelligent NoC design framework which introduces architectural innovations and uses reinforcement learning to manage the design complexity and simultaneously optimize performance, energy-efficiency, and reliability in a holistic manner. IntelliNoC integrates three NoC architectural techniques: (1) multifunction adaptive channels (MFACs) to improve energy-efficiency; (2) adaptive error detection/correction and re-transmission control to enhance reliability; and (3) a stress-relaxing bypass feature which dynamically powers off NoC components to prevent overheating and fatigue. To handle the complex dynamic interactions induced by these techniques, we train a dynamic control policy using Q-learning, with the goal of providing improved fault-tolerance and performance while reducing power consumption and area overhead. Simulation using PARSEC benchmarks shows that our proposed IntelliNoC design improves energy-efficiency by 67% and mean-time-to-failure (MTTF) by 77%, and decreases end-to-end packet latency by 32% and area requirements by 25% over baseline NoC architecture.
KW - Energy-efficiency
KW - Network-on-chip (NoC)
KW - NoC performance
KW - Reinforcement learning
KW - Reliability
UR - http://www.scopus.com/inward/record.url?scp=85069540150&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85069540150&partnerID=8YFLogxK
U2 - 10.1145/3307650.3322274
DO - 10.1145/3307650.3322274
M3 - Conference contribution
AN - SCOPUS:85069540150
T3 - Proceedings - International Symposium on Computer Architecture
SP - 589
EP - 600
BT - ISCA 2019 - Proceedings of the 2019 46th International Symposium on Computer Architecture
PB - Institute of Electrical and Electronics Engineers Inc.
ER -