IntelliNoC: A holistic design framework for energy-efficient and reliable on-chip communication for manycores

Ke Wang, Ahmed Louri, Avinash Karanth, Razvan Bunescu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As technology scales, Network-on-Chips (NoCs), currently being used for on-chip communication in manycore architectures, face several problems including high network latency, excessive power consumption, and low reliability. Simultaneously addressing these problems is proving to be difficult due to the explosion of the design space and the complexity of handling many trade-offs. In this paper, we propose IntelliNoC, an intelligent NoC design framework which introduces architectural innovations and uses reinforcement learning to manage the design complexity and simultaneously optimize performance, energy-efficiency, and reliability in a holistic manner. IntelliNoC integrates three NoC architectural techniques: (1) multifunction adaptive channels (MFACs) to improve energy-efficiency; (2) adaptive error detection/correction and re-transmission control to enhance reliability; and (3) a stress-relaxing bypass feature which dynamically powers off NoC components to prevent overheating and fatigue. To handle the complex dynamic interactions induced by these techniques, we train a dynamic control policy using Q-learning, with the goal of providing improved fault-tolerance and performance while reducing power consumption and area overhead. Simulation using PARSEC benchmarks shows that our proposed IntelliNoC design improves energy-efficiency by 67% and mean-time-to-failure (MTTF) by 77%, and decreases end-to-end packet latency by 32% and area requirements by 25% over baseline NoC architecture.

Original languageEnglish (US)
Title of host publicationISCA 2019 - Proceedings of the 2019 46th International Symposium on Computer Architecture
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages589-600
Number of pages12
ISBN (Electronic)9781450366694
DOIs
StatePublished - Jun 22 2019
Event46th International Symposium on Computer Architecture, ISCA 2019 - Phoenix, United States
Duration: Jun 22 2019Jun 26 2019

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Conference

Conference46th International Symposium on Computer Architecture, ISCA 2019
CountryUnited States
CityPhoenix
Period6/22/196/26/19

Fingerprint

Communication
Energy efficiency
Electric power utilization
Error detection
Reinforcement learning
Fault tolerance
Explosions
Innovation
Network-on-chip
Fatigue of materials

Keywords

  • Energy-efficiency
  • Network-on-chip (NoC)
  • NoC performance
  • Reinforcement learning
  • Reliability

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Wang, K., Louri, A., Karanth, A., & Bunescu, R. (2019). IntelliNoC: A holistic design framework for energy-efficient and reliable on-chip communication for manycores. In ISCA 2019 - Proceedings of the 2019 46th International Symposium on Computer Architecture (pp. 589-600). (Proceedings - International Symposium on Computer Architecture). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3307650.3322274

IntelliNoC : A holistic design framework for energy-efficient and reliable on-chip communication for manycores. / Wang, Ke; Louri, Ahmed; Karanth, Avinash; Bunescu, Razvan.

ISCA 2019 - Proceedings of the 2019 46th International Symposium on Computer Architecture. Institute of Electrical and Electronics Engineers Inc., 2019. p. 589-600 (Proceedings - International Symposium on Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wang, K, Louri, A, Karanth, A & Bunescu, R 2019, IntelliNoC: A holistic design framework for energy-efficient and reliable on-chip communication for manycores. in ISCA 2019 - Proceedings of the 2019 46th International Symposium on Computer Architecture. Proceedings - International Symposium on Computer Architecture, Institute of Electrical and Electronics Engineers Inc., pp. 589-600, 46th International Symposium on Computer Architecture, ISCA 2019, Phoenix, United States, 6/22/19. https://doi.org/10.1145/3307650.3322274
Wang K, Louri A, Karanth A, Bunescu R. IntelliNoC: A holistic design framework for energy-efficient and reliable on-chip communication for manycores. In ISCA 2019 - Proceedings of the 2019 46th International Symposium on Computer Architecture. Institute of Electrical and Electronics Engineers Inc. 2019. p. 589-600. (Proceedings - International Symposium on Computer Architecture). https://doi.org/10.1145/3307650.3322274
Wang, Ke ; Louri, Ahmed ; Karanth, Avinash ; Bunescu, Razvan. / IntelliNoC : A holistic design framework for energy-efficient and reliable on-chip communication for manycores. ISCA 2019 - Proceedings of the 2019 46th International Symposium on Computer Architecture. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 589-600 (Proceedings - International Symposium on Computer Architecture).
@inproceedings{ac7a79af3b0c42a3900eb03a701eb613,
title = "IntelliNoC: A holistic design framework for energy-efficient and reliable on-chip communication for manycores",
abstract = "As technology scales, Network-on-Chips (NoCs), currently being used for on-chip communication in manycore architectures, face several problems including high network latency, excessive power consumption, and low reliability. Simultaneously addressing these problems is proving to be difficult due to the explosion of the design space and the complexity of handling many trade-offs. In this paper, we propose IntelliNoC, an intelligent NoC design framework which introduces architectural innovations and uses reinforcement learning to manage the design complexity and simultaneously optimize performance, energy-efficiency, and reliability in a holistic manner. IntelliNoC integrates three NoC architectural techniques: (1) multifunction adaptive channels (MFACs) to improve energy-efficiency; (2) adaptive error detection/correction and re-transmission control to enhance reliability; and (3) a stress-relaxing bypass feature which dynamically powers off NoC components to prevent overheating and fatigue. To handle the complex dynamic interactions induced by these techniques, we train a dynamic control policy using Q-learning, with the goal of providing improved fault-tolerance and performance while reducing power consumption and area overhead. Simulation using PARSEC benchmarks shows that our proposed IntelliNoC design improves energy-efficiency by 67{\%} and mean-time-to-failure (MTTF) by 77{\%}, and decreases end-to-end packet latency by 32{\%} and area requirements by 25{\%} over baseline NoC architecture.",
keywords = "Energy-efficiency, Network-on-chip (NoC), NoC performance, Reinforcement learning, Reliability",
author = "Ke Wang and Ahmed Louri and Avinash Karanth and Razvan Bunescu",
year = "2019",
month = "6",
day = "22",
doi = "10.1145/3307650.3322274",
language = "English (US)",
series = "Proceedings - International Symposium on Computer Architecture",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "589--600",
booktitle = "ISCA 2019 - Proceedings of the 2019 46th International Symposium on Computer Architecture",

}

TY - GEN

T1 - IntelliNoC

T2 - A holistic design framework for energy-efficient and reliable on-chip communication for manycores

AU - Wang, Ke

AU - Louri, Ahmed

AU - Karanth, Avinash

AU - Bunescu, Razvan

PY - 2019/6/22

Y1 - 2019/6/22

N2 - As technology scales, Network-on-Chips (NoCs), currently being used for on-chip communication in manycore architectures, face several problems including high network latency, excessive power consumption, and low reliability. Simultaneously addressing these problems is proving to be difficult due to the explosion of the design space and the complexity of handling many trade-offs. In this paper, we propose IntelliNoC, an intelligent NoC design framework which introduces architectural innovations and uses reinforcement learning to manage the design complexity and simultaneously optimize performance, energy-efficiency, and reliability in a holistic manner. IntelliNoC integrates three NoC architectural techniques: (1) multifunction adaptive channels (MFACs) to improve energy-efficiency; (2) adaptive error detection/correction and re-transmission control to enhance reliability; and (3) a stress-relaxing bypass feature which dynamically powers off NoC components to prevent overheating and fatigue. To handle the complex dynamic interactions induced by these techniques, we train a dynamic control policy using Q-learning, with the goal of providing improved fault-tolerance and performance while reducing power consumption and area overhead. Simulation using PARSEC benchmarks shows that our proposed IntelliNoC design improves energy-efficiency by 67% and mean-time-to-failure (MTTF) by 77%, and decreases end-to-end packet latency by 32% and area requirements by 25% over baseline NoC architecture.

AB - As technology scales, Network-on-Chips (NoCs), currently being used for on-chip communication in manycore architectures, face several problems including high network latency, excessive power consumption, and low reliability. Simultaneously addressing these problems is proving to be difficult due to the explosion of the design space and the complexity of handling many trade-offs. In this paper, we propose IntelliNoC, an intelligent NoC design framework which introduces architectural innovations and uses reinforcement learning to manage the design complexity and simultaneously optimize performance, energy-efficiency, and reliability in a holistic manner. IntelliNoC integrates three NoC architectural techniques: (1) multifunction adaptive channels (MFACs) to improve energy-efficiency; (2) adaptive error detection/correction and re-transmission control to enhance reliability; and (3) a stress-relaxing bypass feature which dynamically powers off NoC components to prevent overheating and fatigue. To handle the complex dynamic interactions induced by these techniques, we train a dynamic control policy using Q-learning, with the goal of providing improved fault-tolerance and performance while reducing power consumption and area overhead. Simulation using PARSEC benchmarks shows that our proposed IntelliNoC design improves energy-efficiency by 67% and mean-time-to-failure (MTTF) by 77%, and decreases end-to-end packet latency by 32% and area requirements by 25% over baseline NoC architecture.

KW - Energy-efficiency

KW - Network-on-chip (NoC)

KW - NoC performance

KW - Reinforcement learning

KW - Reliability

UR - http://www.scopus.com/inward/record.url?scp=85069540150&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85069540150&partnerID=8YFLogxK

U2 - 10.1145/3307650.3322274

DO - 10.1145/3307650.3322274

M3 - Conference contribution

AN - SCOPUS:85069540150

T3 - Proceedings - International Symposium on Computer Architecture

SP - 589

EP - 600

BT - ISCA 2019 - Proceedings of the 2019 46th International Symposium on Computer Architecture

PB - Institute of Electrical and Electronics Engineers Inc.

ER -