IP protection for VLSI designs via watermarking of routes

N. Narayan, R. D. Newbould, J. D. Carothers, J. J. Rodriguez, W. T. Holman

Research output: Contribution to journalConference article

33 Scopus citations

Abstract

Intellectual property protection (IPP) has become a major concern in today's CAD and ASIC/SOC industries. This paper presents a watermarking technique for IPP at the physical design level. We propose a method for embedding a watermark by modifying the number of vias or bends used to route the nets in a design. This technique is applicable to digital, analog and mixed-signal design, and has the ability to accommodate the noise tolerance and design intricacies of each.

Original languageEnglish (US)
Pages (from-to)406-410
Number of pages5
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
StatePublished - Jan 1 2001
Event14th Annual IEEE International ASIC/SOC Conference- System-on-Chip in a Networked World- - Arlington, VA, United States
Duration: Sep 12 2001Sep 15 2001

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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