IP protection for VLSI designs via watermarking of routes

N. Narayan, R. D. Newbould, J. D. Carothers, Jeffrey J Rodriguez, W. T. Holman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

32 Citations (Scopus)

Abstract

Intellectual property protection (IPP) has become a major concern in today's CAD and ASIC/SOC industries. This paper presents a watermarking technique for IPP at the physical design level. We propose a method for embedding a watermark by modifying the number of vias or bends used to route the nets in a design. This technique is applicable to digital, analog and mixed-signal design, and has the ability to accommodate the noise tolerance and design intricacies of each.

Original languageEnglish (US)
Title of host publicationProceedings of the Annual IEEE International ASIC Conference and Exhibit
EditorsP.R. Mukund, J. Chickanosky, R.K. Krishnamurthy
Pages406-410
Number of pages5
StatePublished - 2001
Event14th Annual IEEE International ASIC/SOC Conference- System-on-Chip in a Networked World- - Arlington, VA, United States
Duration: Sep 12 2001Sep 15 2001

Other

Other14th Annual IEEE International ASIC/SOC Conference- System-on-Chip in a Networked World-
CountryUnited States
CityArlington, VA
Period9/12/019/15/01

Fingerprint

Watermarking
Intellectual property
Application specific integrated circuits
Computer aided design
Industry

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Narayan, N., Newbould, R. D., Carothers, J. D., Rodriguez, J. J., & Holman, W. T. (2001). IP protection for VLSI designs via watermarking of routes. In P. R. Mukund, J. Chickanosky, & R. K. Krishnamurthy (Eds.), Proceedings of the Annual IEEE International ASIC Conference and Exhibit (pp. 406-410)

IP protection for VLSI designs via watermarking of routes. / Narayan, N.; Newbould, R. D.; Carothers, J. D.; Rodriguez, Jeffrey J; Holman, W. T.

Proceedings of the Annual IEEE International ASIC Conference and Exhibit. ed. / P.R. Mukund; J. Chickanosky; R.K. Krishnamurthy. 2001. p. 406-410.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Narayan, N, Newbould, RD, Carothers, JD, Rodriguez, JJ & Holman, WT 2001, IP protection for VLSI designs via watermarking of routes. in PR Mukund, J Chickanosky & RK Krishnamurthy (eds), Proceedings of the Annual IEEE International ASIC Conference and Exhibit. pp. 406-410, 14th Annual IEEE International ASIC/SOC Conference- System-on-Chip in a Networked World-, Arlington, VA, United States, 9/12/01.
Narayan N, Newbould RD, Carothers JD, Rodriguez JJ, Holman WT. IP protection for VLSI designs via watermarking of routes. In Mukund PR, Chickanosky J, Krishnamurthy RK, editors, Proceedings of the Annual IEEE International ASIC Conference and Exhibit. 2001. p. 406-410
Narayan, N. ; Newbould, R. D. ; Carothers, J. D. ; Rodriguez, Jeffrey J ; Holman, W. T. / IP protection for VLSI designs via watermarking of routes. Proceedings of the Annual IEEE International ASIC Conference and Exhibit. editor / P.R. Mukund ; J. Chickanosky ; R.K. Krishnamurthy. 2001. pp. 406-410
@inproceedings{c95cb1d6cba7428e88d3e1c249049bad,
title = "IP protection for VLSI designs via watermarking of routes",
abstract = "Intellectual property protection (IPP) has become a major concern in today's CAD and ASIC/SOC industries. This paper presents a watermarking technique for IPP at the physical design level. We propose a method for embedding a watermark by modifying the number of vias or bends used to route the nets in a design. This technique is applicable to digital, analog and mixed-signal design, and has the ability to accommodate the noise tolerance and design intricacies of each.",
author = "N. Narayan and Newbould, {R. D.} and Carothers, {J. D.} and Rodriguez, {Jeffrey J} and Holman, {W. T.}",
year = "2001",
language = "English (US)",
pages = "406--410",
editor = "P.R. Mukund and J. Chickanosky and R.K. Krishnamurthy",
booktitle = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

}

TY - GEN

T1 - IP protection for VLSI designs via watermarking of routes

AU - Narayan, N.

AU - Newbould, R. D.

AU - Carothers, J. D.

AU - Rodriguez, Jeffrey J

AU - Holman, W. T.

PY - 2001

Y1 - 2001

N2 - Intellectual property protection (IPP) has become a major concern in today's CAD and ASIC/SOC industries. This paper presents a watermarking technique for IPP at the physical design level. We propose a method for embedding a watermark by modifying the number of vias or bends used to route the nets in a design. This technique is applicable to digital, analog and mixed-signal design, and has the ability to accommodate the noise tolerance and design intricacies of each.

AB - Intellectual property protection (IPP) has become a major concern in today's CAD and ASIC/SOC industries. This paper presents a watermarking technique for IPP at the physical design level. We propose a method for embedding a watermark by modifying the number of vias or bends used to route the nets in a design. This technique is applicable to digital, analog and mixed-signal design, and has the ability to accommodate the noise tolerance and design intricacies of each.

UR - http://www.scopus.com/inward/record.url?scp=0034771122&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034771122&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0034771122

SP - 406

EP - 410

BT - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

A2 - Mukund, P.R.

A2 - Chickanosky, J.

A2 - Krishnamurthy, R.K.

ER -