Latency, power, and security optimization in distributed reconfigurable embedded systems

Hyunsuk Nam, Roman L Lysecky

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

Distributed embedded systems are increasingly prevalent in numerous applications, and with pervasive network access within these systems, security is also a critical design concern. In this paper, we present a modeling and optimization framework for distributed reconfigurable embedded systems, which maps tasks on a distributed embedded system with the goal of optimizing latency, energy, and/or security across all computing and communication levels. The proposed modeling framework for dataflow applications integrates models for computational latency, security levels for inter-task and intra-task communication, communication latency, and power consumption. We evaluate the proposed methodology using a video-based object detection and tracking application.

Original languageEnglish (US)
Title of host publicationProceedings - 2016 IEEE 30th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2016
PublisherIEEE Computer Society
Pages124-131
Number of pages8
Volume2016-August
ISBN (Electronic)9781509021406
DOIs
StatePublished - Aug 2 2016
Event30th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2016 - Chicago, United States
Duration: May 23 2016May 27 2016

Other

Other30th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2016
CountryUnited States
CityChicago
Period5/23/165/27/16

Keywords

  • Co-design modeling
  • Design space exploration
  • Distributed embedded systems
  • Dynamic optimization
  • Security

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Networks and Communications
  • Hardware and Architecture
  • Software

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