Linear-time, optimal code scheduling for delayed-load architectures

Todd A. Proebsting, Charles N. Fischer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

A fast, optimal code scheduling algorithm for processors with a delayed load of 1 instruction cycle is described. The algorithm minimizes both execution time and register use and runs in time proportional to the size of the expression tree. Extensions that spill registers when too few are available are also presented. The algorithm also performs very well for delayed loads of greater than 1 instruction cycle. For machines with load delays greater than 1, bounds are given for the minimal number of registers needed for optimally evaluating an expression tree.

Original languageEnglish (US)
Title of host publicationProceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)
PublisherAssociation for Computing Machinery
Pages256-267
Number of pages12
ISBN (Print)0897914287
DOIs
StatePublished - May 1 1991
Externally publishedYes
Event1991 ACM SIGPLAN 1991 Conference on Programming Language Design and Implementation, PLDI 1991 - Ottawa, Canada
Duration: Jun 24 1991Jun 28 1991

Publication series

NameProceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)

Other

Other1991 ACM SIGPLAN 1991 Conference on Programming Language Design and Implementation, PLDI 1991
CountryCanada
CityOttawa
Period6/24/916/28/91

ASJC Scopus subject areas

  • Software

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  • Cite this

    Proebsting, T. A., & Fischer, C. N. (1991). Linear-time, optimal code scheduling for delayed-load architectures. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI) (pp. 256-267). (Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)). Association for Computing Machinery. https://doi.org/10.1145/113445.113467