Low complexity memory architectures based on LDPC codes: Benefits and disadvantages

Bane V Vasic, Predrag Ivaniš, Srdan Brkic

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

In this paper we investigate the problem of information storage in inherently unreliable memory cells. In order to increase the memory reliability, information is stored in memory cells as a codeword of a low-density parity-check (LDPC) code, while the memory content is updated periodically by an error correction scheme. We first present an overview on the state-of-the memory architectures based on LDPC codes, and then asses the benefits of using the coded architectures expressed through the increased reliability. In addition, we provide upper bounds on the complexity of such memories.

Original languageEnglish (US)
Title of host publication2015 12th International Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Services, TELSIKS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages11-18
Number of pages8
ISBN (Print)9781467375160
DOIs
Publication statusPublished - Dec 14 2015
Event12th International Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Services, TELSIKS 2015 - Nis, Serbia
Duration: Oct 14 2015Oct 17 2015

Other

Other12th International Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Services, TELSIKS 2015
CountrySerbia
CityNis
Period10/14/1510/17/15

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ASJC Scopus subject areas

  • Communication
  • Computer Networks and Communications

Cite this

Vasic, B. V., Ivaniš, P., & Brkic, S. (2015). Low complexity memory architectures based on LDPC codes: Benefits and disadvantages. In 2015 12th International Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Services, TELSIKS 2015 (pp. 11-18). [7357727] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TELSKS.2015.7357727