Abstract
We propose a method for watermarking, called `fingermarking,' for integrated circuit design at the physical design level. The watermark is embedded in the transistor layout, making our method applicable to digital, analog, and mixed-signal SOC designs. We show that a robust watermark can be applied to many designs, and can be implemented with little or no cost in circuit area or performance.
Original language | English (US) |
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Pages (from-to) | 136-140 |
Number of pages | 5 |
Journal | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
State | Published - Jan 1 2000 |
Event | Proceedings of the 13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA Duration: Sep 13 2000 → Sep 16 2000 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering