Abstract
We propose a method for watermarking, called `fingermarking,' for integrated circuit design at the physical design level. The watermark is embedded in the transistor layout, making our method applicable to digital, analog, and mixed-signal SOC designs. We show that a robust watermark can be applied to many designs, and can be implemented with little or no cost in circuit area or performance.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
| Publisher | IEEE |
| Pages | 136-140 |
| Number of pages | 5 |
| State | Published - 2000 |
| Event | Proceedings of the 13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA Duration: Sep 13 2000 → Sep 16 2000 |
Other
| Other | Proceedings of the 13th Annual IEEE International ASIC/SOC Conference |
|---|---|
| City | Arlington, VA, USA |
| Period | 9/13/00 → 9/16/00 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Low level watermarking of VLSI designs for intellectual property protection. / Irby, David L.; Newbould, Rexford D.; Carothers, Jo Dale; Rodriguez, Jeffrey J; Holman, W. Timothy.
Proceedings of the Annual IEEE International ASIC Conference and Exhibit. IEEE, 2000. p. 136-140.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Low level watermarking of VLSI designs for intellectual property protection
AU - Irby, David L.
AU - Newbould, Rexford D.
AU - Carothers, Jo Dale
AU - Rodriguez, Jeffrey J
AU - Holman, W. Timothy
PY - 2000
Y1 - 2000
N2 - We propose a method for watermarking, called `fingermarking,' for integrated circuit design at the physical design level. The watermark is embedded in the transistor layout, making our method applicable to digital, analog, and mixed-signal SOC designs. We show that a robust watermark can be applied to many designs, and can be implemented with little or no cost in circuit area or performance.
AB - We propose a method for watermarking, called `fingermarking,' for integrated circuit design at the physical design level. The watermark is embedded in the transistor layout, making our method applicable to digital, analog, and mixed-signal SOC designs. We show that a robust watermark can be applied to many designs, and can be implemented with little or no cost in circuit area or performance.
UR - http://www.scopus.com/inward/record.url?scp=0033680790&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0033680790&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0033680790
SP - 136
EP - 140
BT - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
PB - IEEE
ER -