Low level watermarking of VLSI designs for intellectual property protection

David L. Irby, Rexford D. Newbould, Jo Dale Carothers, Jeffrey J. Rodriguez, W. Timothy Holman

Research output: Contribution to journalConference article

13 Scopus citations

Abstract

We propose a method for watermarking, called `fingermarking,' for integrated circuit design at the physical design level. The watermark is embedded in the transistor layout, making our method applicable to digital, analog, and mixed-signal SOC designs. We show that a robust watermark can be applied to many designs, and can be implemented with little or no cost in circuit area or performance.

Original languageEnglish (US)
Pages (from-to)136-140
Number of pages5
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
StatePublished - Jan 1 2000
EventProceedings of the 13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA
Duration: Sep 13 2000Sep 16 2000

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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