Low level watermarking of VLSI designs for intellectual property protection

David L. Irby, Rexford D. Newbould, Jo Dale Carothers, Jeffrey J Rodriguez, W. Timothy Holman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

We propose a method for watermarking, called `fingermarking,' for integrated circuit design at the physical design level. The watermark is embedded in the transistor layout, making our method applicable to digital, analog, and mixed-signal SOC designs. We show that a robust watermark can be applied to many designs, and can be implemented with little or no cost in circuit area or performance.

Original languageEnglish (US)
Title of host publicationProceedings of the Annual IEEE International ASIC Conference and Exhibit
PublisherIEEE
Pages136-140
Number of pages5
StatePublished - 2000
EventProceedings of the 13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA
Duration: Sep 13 2000Sep 16 2000

Other

OtherProceedings of the 13th Annual IEEE International ASIC/SOC Conference
CityArlington, VA, USA
Period9/13/009/16/00

Fingerprint

Intellectual property
Watermarking
Transistors
Networks (circuits)
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Irby, D. L., Newbould, R. D., Carothers, J. D., Rodriguez, J. J., & Holman, W. T. (2000). Low level watermarking of VLSI designs for intellectual property protection. In Proceedings of the Annual IEEE International ASIC Conference and Exhibit (pp. 136-140). IEEE.

Low level watermarking of VLSI designs for intellectual property protection. / Irby, David L.; Newbould, Rexford D.; Carothers, Jo Dale; Rodriguez, Jeffrey J; Holman, W. Timothy.

Proceedings of the Annual IEEE International ASIC Conference and Exhibit. IEEE, 2000. p. 136-140.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Irby, DL, Newbould, RD, Carothers, JD, Rodriguez, JJ & Holman, WT 2000, Low level watermarking of VLSI designs for intellectual property protection. in Proceedings of the Annual IEEE International ASIC Conference and Exhibit. IEEE, pp. 136-140, Proceedings of the 13th Annual IEEE International ASIC/SOC Conference, Arlington, VA, USA, 9/13/00.
Irby DL, Newbould RD, Carothers JD, Rodriguez JJ, Holman WT. Low level watermarking of VLSI designs for intellectual property protection. In Proceedings of the Annual IEEE International ASIC Conference and Exhibit. IEEE. 2000. p. 136-140
Irby, David L. ; Newbould, Rexford D. ; Carothers, Jo Dale ; Rodriguez, Jeffrey J ; Holman, W. Timothy. / Low level watermarking of VLSI designs for intellectual property protection. Proceedings of the Annual IEEE International ASIC Conference and Exhibit. IEEE, 2000. pp. 136-140
@inproceedings{f67ceb8637b84058927b907119b62792,
title = "Low level watermarking of VLSI designs for intellectual property protection",
abstract = "We propose a method for watermarking, called `fingermarking,' for integrated circuit design at the physical design level. The watermark is embedded in the transistor layout, making our method applicable to digital, analog, and mixed-signal SOC designs. We show that a robust watermark can be applied to many designs, and can be implemented with little or no cost in circuit area or performance.",
author = "Irby, {David L.} and Newbould, {Rexford D.} and Carothers, {Jo Dale} and Rodriguez, {Jeffrey J} and Holman, {W. Timothy}",
year = "2000",
language = "English (US)",
pages = "136--140",
booktitle = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",
publisher = "IEEE",

}

TY - GEN

T1 - Low level watermarking of VLSI designs for intellectual property protection

AU - Irby, David L.

AU - Newbould, Rexford D.

AU - Carothers, Jo Dale

AU - Rodriguez, Jeffrey J

AU - Holman, W. Timothy

PY - 2000

Y1 - 2000

N2 - We propose a method for watermarking, called `fingermarking,' for integrated circuit design at the physical design level. The watermark is embedded in the transistor layout, making our method applicable to digital, analog, and mixed-signal SOC designs. We show that a robust watermark can be applied to many designs, and can be implemented with little or no cost in circuit area or performance.

AB - We propose a method for watermarking, called `fingermarking,' for integrated circuit design at the physical design level. The watermark is embedded in the transistor layout, making our method applicable to digital, analog, and mixed-signal SOC designs. We show that a robust watermark can be applied to many designs, and can be implemented with little or no cost in circuit area or performance.

UR - http://www.scopus.com/inward/record.url?scp=0033680790&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033680790&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0033680790

SP - 136

EP - 140

BT - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

PB - IEEE

ER -