Low-power warp processor for power efficient high-performance embedded systems

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels within the software as custom hardware circuits in an on-chip FPGA. However, the original warp processor design was primarily performance-driven and did not focus on power consumption, which is becoming an increasingly important design constraint. Focusing on power consumption, we present an alternative low-power warp processor design and methodology that can dynamically and transparently reduce power consumption of an executing application with no degradation in system performance, achieving an average reduction in power consumption of 74%. We further demonstrate the flexibility of this approach to provide dynamic control between high-performance and low-power consumption.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
Pages141-146
Number of pages6
DOIs
StatePublished - 2007
Event2007 Design, Automation and Test in Europe Conference and Exhibition - Nice Acropolis, France
Duration: Apr 16 2007Apr 20 2007

Other

Other2007 Design, Automation and Test in Europe Conference and Exhibition
CountryFrance
CityNice Acropolis
Period4/16/074/20/07

Fingerprint

Embedded systems
Electric power utilization
Field programmable gate arrays (FPGA)
Hardware
Degradation
Networks (circuits)

Keywords

  • Dynamically adaptable systems
  • Embedded systems
  • Hardware/software partitioning
  • Low-power
  • Warp processing

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Lysecky, R. L. (2007). Low-power warp processor for power efficient high-performance embedded systems. In Proceedings -Design, Automation and Test in Europe, DATE (pp. 141-146). [4211786] https://doi.org/10.1109/DATE.2007.364581

Low-power warp processor for power efficient high-performance embedded systems. / Lysecky, Roman L.

Proceedings -Design, Automation and Test in Europe, DATE. 2007. p. 141-146 4211786.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lysecky, RL 2007, Low-power warp processor for power efficient high-performance embedded systems. in Proceedings -Design, Automation and Test in Europe, DATE., 4211786, pp. 141-146, 2007 Design, Automation and Test in Europe Conference and Exhibition, Nice Acropolis, France, 4/16/07. https://doi.org/10.1109/DATE.2007.364581
Lysecky RL. Low-power warp processor for power efficient high-performance embedded systems. In Proceedings -Design, Automation and Test in Europe, DATE. 2007. p. 141-146. 4211786 https://doi.org/10.1109/DATE.2007.364581
Lysecky, Roman L. / Low-power warp processor for power efficient high-performance embedded systems. Proceedings -Design, Automation and Test in Europe, DATE. 2007. pp. 141-146
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