Mapping 1D-FFT on an energy efficient 3D FPGA-DRAM architecture

Peter Gadfort, Aravind Dasu, Ali Akoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The one-dimensional Fast Fourier Transform (1D-FFT) is a fast method of computing the Discrete Fourier Transform (DFT) that is pervasive in signal processing applications. In this paper we present details on the mapping of the 1D-FFT on a power efficient 3D FPGA-DRAM architecture [1], with four data sizes: 256pt, 1024pt, 4096pt and 32768pt to achieve 29 GFLOPs/W with a 65nm technology.

Original languageEnglish (US)
Title of host publication2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781467385688
DOIs
StatePublished - Nov 24 2015
Event4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Berkeley, United States
Duration: Oct 1 2015Oct 2 2015

Other

Other4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015
CountryUnited States
CityBerkeley
Period10/1/1510/2/15

Keywords

  • Adders
  • Computer architecture
  • Energy efficiency
  • Field programmable gate arrays
  • Ports (Computers)
  • Random access memory
  • Three-dimensional displays

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Gadfort, P., Dasu, A., & Akoglu, A. (2015). Mapping 1D-FFT on an energy efficient 3D FPGA-DRAM architecture. In 2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings [7336816] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/E3S.2015.7336816