Mapping nested loop algorithms into fault-tolerant systolic array architectures

M. O. Esonu, A. J. Al-Khalili, Salim A Hariri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Progress in VLSI and WSI technologies has resulted in the manufacture of special purpose VLSI chips with multiple copies of low-cost processors. These processors can be used to design high performance systems such as systolic arrays. This paper proposes a new systematic approach which can be used to detect and correct errors in systolic array architectures. The approach relies on Space-Time mapping of algorithms into systolic arrays. Fault-tolerant algorithms are designed by introducing redundant computations at the algorithmic level. This is done by deriving several versions of a given algorithm, each of which can be mapped into respective systolic architecture. Fault-tolerant systolic array is constructed by merging the corresponding systolic array of several versions of the algorithm.

Original languageEnglish (US)
Title of host publicationIEEE International Conference on Algorithms and Architectures for Parallel Processing
PublisherIEEE
Pages30-39
Number of pages10
Volume1
Publication statusPublished - 1995
Externally publishedYes
EventProceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2) - Brisbane, Aust
Duration: Apr 19 1995Apr 21 1995

Other

OtherProceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2)
CityBrisbane, Aust
Period4/19/954/21/95

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ASJC Scopus subject areas

  • Computer Science(all)
  • Engineering(all)

Cite this

Esonu, M. O., Al-Khalili, A. J., & Hariri, S. A. (1995). Mapping nested loop algorithms into fault-tolerant systolic array architectures. In IEEE International Conference on Algorithms and Architectures for Parallel Processing (Vol. 1, pp. 30-39). IEEE.