Monopoles Loaded with 3-D-Printed Dielectrics for Future Wireless Intra-Chip Communications

Junqiang Wu, Avinash Kodi, Savas Kaya, Ahmed Louri, Hao Xin

Research output: Contribution to journalArticle

14 Scopus citations

Abstract

We propose a novel antenna design enabled by 3-D printing technology for future wireless intra-chip interconnects aiming at applications of multicore architectures and system-on-chips (SoCs). In our proposed design we use vertical quarter-wavelength monopoles at 160 GHz on a ground plane to avoid low antenna radiation efficiency caused by the silicon substrate. The monopoles are surrounded by a specially-designed dielectric property distribution. This additional degree of freedom in design enabled by 3-D printing technology is used to tailor the electromagnetic wave propagation. As a result, the desired wireless link gain is enhanced and the undesired spatial crosstalk is reduced. Simulation results show that the proposed dielectric loading approach improves the desired link gain by 8-15 dB and reduces the crosstalk by 9-23 dB from 155 GHz to 165 GHz. As a proof-of-concept, a 60 GHz prototype is designed, fabricated and characterized. Our measurement results match the simulation results and demonstrate 10-18 dB improvement of the desired link gain and 10-30 dB reduction in the crosstalk from 55 GHz to 61 GHz. The demonstrated transmission loss of the desired link at a distance of 17 mm is only 15 dB, which is over 10 dB better than the previously reported work.

Original languageEnglish (US)
JournalIEEE Transactions on Antennas and Propagation
DOIs
Publication statusAccepted/In press - Oct 1 2017

    Fingerprint

Keywords

  • 3-D printing
  • Antennas
  • antennas
  • Computer architecture
  • Dielectrics
  • electromagnetic propagation
  • Gain
  • interconnect
  • intra-chip communication
  • multiprocessor interconnection
  • network on chip
  • Silicon
  • Substrates
  • Wireless communication

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this