Multi-mode low-latency software-defined error correction for data centers

Fakhreddine Ghaffari, Ali Akoglu, Bane V Vasic, David Declercq

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Flash memories are gaining prominence for utilizing in large scale data centers (DCs) due to their high memory density, low power consumption and heat dissipation, and high access speed characteristics. The rate of degradation for a flash memory is largely affected by the amount and frequency of the erase/write operations, which is a challenge in the DC context that serves dynamically changing workloads. Adaptive Error Correction Code (AECC) schemes have been introduced for changing the error correction algorithm based on the reliability state of the flash. In this study we show that hard decision (bit-flipping) and soft decision decoding (Belief Propagation) class of algorithms for Low Density Parity Check (LDPC) decoders complement each other for utilizing in the flash based DCs in order to meet the dynamically changing reliability level. We propose a new family of ECC to improve the reliability of flash memory. Our Monte-Carlo simulations and Field Programmable Gate Array (FPGA) based hardware implementation analysis show that LDPC decoders are suitable for balancing the throughput, decoding performance and reliability requirements in DCs.

Original languageEnglish (US)
Title of host publication2017 26th International Conference on Computer Communications and Networks, ICCCN 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509029914
DOIs
StatePublished - Sep 14 2017
Event26th International Conference on Computer Communications and Networks, ICCCN 2017 - Vancouver, Canada
Duration: Jul 31 2017Aug 3 2017

Other

Other26th International Conference on Computer Communications and Networks, ICCCN 2017
CountryCanada
CityVancouver
Period7/31/178/3/17

Fingerprint

Data Center
Error correction
Error Correction
Flash Memory
Flash memory
Latency
Software
Flash
Parity
Decoding
Belief Propagation
Hardware Implementation
Heat losses
Balancing
Field Programmable Gate Array
Power Consumption
Workload
Field programmable gate arrays (FPGA)
Dissipation
Degradation

Keywords

  • Data centers
  • FPGA architecture
  • Hardware complexity/decoding performance trade-off
  • High-performance hard-decision and soft decision LDPC decoders
  • Low-latency LDPC decoder

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Networks and Communications
  • Software
  • Management of Technology and Innovation
  • Information Systems and Management
  • Safety, Risk, Reliability and Quality
  • Media Technology
  • Control and Optimization

Cite this

Ghaffari, F., Akoglu, A., Vasic, B. V., & Declercq, D. (2017). Multi-mode low-latency software-defined error correction for data centers. In 2017 26th International Conference on Computer Communications and Networks, ICCCN 2017 [8038467] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCCN.2017.8038467

Multi-mode low-latency software-defined error correction for data centers. / Ghaffari, Fakhreddine; Akoglu, Ali; Vasic, Bane V; Declercq, David.

2017 26th International Conference on Computer Communications and Networks, ICCCN 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 8038467.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ghaffari, F, Akoglu, A, Vasic, BV & Declercq, D 2017, Multi-mode low-latency software-defined error correction for data centers. in 2017 26th International Conference on Computer Communications and Networks, ICCCN 2017., 8038467, Institute of Electrical and Electronics Engineers Inc., 26th International Conference on Computer Communications and Networks, ICCCN 2017, Vancouver, Canada, 7/31/17. https://doi.org/10.1109/ICCCN.2017.8038467
Ghaffari F, Akoglu A, Vasic BV, Declercq D. Multi-mode low-latency software-defined error correction for data centers. In 2017 26th International Conference on Computer Communications and Networks, ICCCN 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 8038467 https://doi.org/10.1109/ICCCN.2017.8038467
Ghaffari, Fakhreddine ; Akoglu, Ali ; Vasic, Bane V ; Declercq, David. / Multi-mode low-latency software-defined error correction for data centers. 2017 26th International Conference on Computer Communications and Networks, ICCCN 2017. Institute of Electrical and Electronics Engineers Inc., 2017.
@inproceedings{8dcfd83b2c424a2fbb14e785c92e3ab6,
title = "Multi-mode low-latency software-defined error correction for data centers",
abstract = "Flash memories are gaining prominence for utilizing in large scale data centers (DCs) due to their high memory density, low power consumption and heat dissipation, and high access speed characteristics. The rate of degradation for a flash memory is largely affected by the amount and frequency of the erase/write operations, which is a challenge in the DC context that serves dynamically changing workloads. Adaptive Error Correction Code (AECC) schemes have been introduced for changing the error correction algorithm based on the reliability state of the flash. In this study we show that hard decision (bit-flipping) and soft decision decoding (Belief Propagation) class of algorithms for Low Density Parity Check (LDPC) decoders complement each other for utilizing in the flash based DCs in order to meet the dynamically changing reliability level. We propose a new family of ECC to improve the reliability of flash memory. Our Monte-Carlo simulations and Field Programmable Gate Array (FPGA) based hardware implementation analysis show that LDPC decoders are suitable for balancing the throughput, decoding performance and reliability requirements in DCs.",
keywords = "Data centers, FPGA architecture, Hardware complexity/decoding performance trade-off, High-performance hard-decision and soft decision LDPC decoders, Low-latency LDPC decoder",
author = "Fakhreddine Ghaffari and Ali Akoglu and Vasic, {Bane V} and David Declercq",
year = "2017",
month = "9",
day = "14",
doi = "10.1109/ICCCN.2017.8038467",
language = "English (US)",
booktitle = "2017 26th International Conference on Computer Communications and Networks, ICCCN 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

TY - GEN

T1 - Multi-mode low-latency software-defined error correction for data centers

AU - Ghaffari, Fakhreddine

AU - Akoglu, Ali

AU - Vasic, Bane V

AU - Declercq, David

PY - 2017/9/14

Y1 - 2017/9/14

N2 - Flash memories are gaining prominence for utilizing in large scale data centers (DCs) due to their high memory density, low power consumption and heat dissipation, and high access speed characteristics. The rate of degradation for a flash memory is largely affected by the amount and frequency of the erase/write operations, which is a challenge in the DC context that serves dynamically changing workloads. Adaptive Error Correction Code (AECC) schemes have been introduced for changing the error correction algorithm based on the reliability state of the flash. In this study we show that hard decision (bit-flipping) and soft decision decoding (Belief Propagation) class of algorithms for Low Density Parity Check (LDPC) decoders complement each other for utilizing in the flash based DCs in order to meet the dynamically changing reliability level. We propose a new family of ECC to improve the reliability of flash memory. Our Monte-Carlo simulations and Field Programmable Gate Array (FPGA) based hardware implementation analysis show that LDPC decoders are suitable for balancing the throughput, decoding performance and reliability requirements in DCs.

AB - Flash memories are gaining prominence for utilizing in large scale data centers (DCs) due to their high memory density, low power consumption and heat dissipation, and high access speed characteristics. The rate of degradation for a flash memory is largely affected by the amount and frequency of the erase/write operations, which is a challenge in the DC context that serves dynamically changing workloads. Adaptive Error Correction Code (AECC) schemes have been introduced for changing the error correction algorithm based on the reliability state of the flash. In this study we show that hard decision (bit-flipping) and soft decision decoding (Belief Propagation) class of algorithms for Low Density Parity Check (LDPC) decoders complement each other for utilizing in the flash based DCs in order to meet the dynamically changing reliability level. We propose a new family of ECC to improve the reliability of flash memory. Our Monte-Carlo simulations and Field Programmable Gate Array (FPGA) based hardware implementation analysis show that LDPC decoders are suitable for balancing the throughput, decoding performance and reliability requirements in DCs.

KW - Data centers

KW - FPGA architecture

KW - Hardware complexity/decoding performance trade-off

KW - High-performance hard-decision and soft decision LDPC decoders

KW - Low-latency LDPC decoder

UR - http://www.scopus.com/inward/record.url?scp=85032261593&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85032261593&partnerID=8YFLogxK

U2 - 10.1109/ICCCN.2017.8038467

DO - 10.1109/ICCCN.2017.8038467

M3 - Conference contribution

BT - 2017 26th International Conference on Computer Communications and Networks, ICCCN 2017

PB - Institute of Electrical and Electronics Engineers Inc.

ER -