Multidimensional and reconfigurable optical interconnects for high-performance computing (HPC) systems

Avinash Kodi Kodi, Ahmed Louri

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

The increasing demand for higher communication bandwidth, reduced power consumption, and increased reliability combined with fundamental electrical signalling limitations is leading the drive for optics as an interconnect technology of choice for high-performance computing (HPC) systems. However, failure in any optical link can completely disrupt communication by isolating processing nodes in HPC systems. Moreover, while static allocation of wavelengths (channels) provides every node with equal opportunity for communication, it can also lead to network congestion for nonuniform traffic patterns. In this paper, we propose a multidimensional optoelectronic architecture, called nD-reconfigurable, all-photonic interconnect for distributed and parallel systems (ndimensional-RAPID) where n can be 1, 2, or 3. nD-RAPID exploits optical architecture and technology design space that simultaneously tackles both fault-tolerance and dynamic bandwidth reallocation (DBR) of system architecture. Fault-tolerance in nD-RAPID is enabled through a multidimensional architecture. DBR is implemented by the row-column switching matrix using silicon-on-insulator (SOI)-based microring resonators that adapts to changes in communication patterns at runtime. Simulation results indicate that nD-RAPID outperformed other electrical networks for most traffic patterns. Results on DBR show that the proposed row-column switch organization significantly improves throughput and latency with a slight increase in electrical power consumption (∼0.4% for the worst case traffic).

Original languageEnglish (US)
Pages (from-to)4634-4641
Number of pages8
JournalJournal of Lightwave Technology
Volume27
Issue number21
DOIs
StatePublished - Nov 1 2009

Fingerprint

optical interconnects
communication
traffic
bandwidth
fault tolerance
congestion
switches
resonators
insulators
photonics
optics
silicon
matrices
wavelengths
simulation

Keywords

  • Fault tolerance
  • Optical interconnections
  • Parallel processing
  • Reconfigurable architectures

ASJC Scopus subject areas

  • Atomic and Molecular Physics, and Optics

Cite this

Multidimensional and reconfigurable optical interconnects for high-performance computing (HPC) systems. / Kodi, Avinash Kodi; Louri, Ahmed.

In: Journal of Lightwave Technology, Vol. 27, No. 21, 01.11.2009, p. 4634-4641.

Research output: Contribution to journalArticle

@article{f684b3522a214c8b93e7e3c4d74f8d23,
title = "Multidimensional and reconfigurable optical interconnects for high-performance computing (HPC) systems",
abstract = "The increasing demand for higher communication bandwidth, reduced power consumption, and increased reliability combined with fundamental electrical signalling limitations is leading the drive for optics as an interconnect technology of choice for high-performance computing (HPC) systems. However, failure in any optical link can completely disrupt communication by isolating processing nodes in HPC systems. Moreover, while static allocation of wavelengths (channels) provides every node with equal opportunity for communication, it can also lead to network congestion for nonuniform traffic patterns. In this paper, we propose a multidimensional optoelectronic architecture, called nD-reconfigurable, all-photonic interconnect for distributed and parallel systems (ndimensional-RAPID) where n can be 1, 2, or 3. nD-RAPID exploits optical architecture and technology design space that simultaneously tackles both fault-tolerance and dynamic bandwidth reallocation (DBR) of system architecture. Fault-tolerance in nD-RAPID is enabled through a multidimensional architecture. DBR is implemented by the row-column switching matrix using silicon-on-insulator (SOI)-based microring resonators that adapts to changes in communication patterns at runtime. Simulation results indicate that nD-RAPID outperformed other electrical networks for most traffic patterns. Results on DBR show that the proposed row-column switch organization significantly improves throughput and latency with a slight increase in electrical power consumption (∼0.4{\%} for the worst case traffic).",
keywords = "Fault tolerance, Optical interconnections, Parallel processing, Reconfigurable architectures",
author = "Kodi, {Avinash Kodi} and Ahmed Louri",
year = "2009",
month = "11",
day = "1",
doi = "10.1109/JLT.2009.2026187",
language = "English (US)",
volume = "27",
pages = "4634--4641",
journal = "Journal of Lightwave Technology",
issn = "0733-8724",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "21",

}

TY - JOUR

T1 - Multidimensional and reconfigurable optical interconnects for high-performance computing (HPC) systems

AU - Kodi, Avinash Kodi

AU - Louri, Ahmed

PY - 2009/11/1

Y1 - 2009/11/1

N2 - The increasing demand for higher communication bandwidth, reduced power consumption, and increased reliability combined with fundamental electrical signalling limitations is leading the drive for optics as an interconnect technology of choice for high-performance computing (HPC) systems. However, failure in any optical link can completely disrupt communication by isolating processing nodes in HPC systems. Moreover, while static allocation of wavelengths (channels) provides every node with equal opportunity for communication, it can also lead to network congestion for nonuniform traffic patterns. In this paper, we propose a multidimensional optoelectronic architecture, called nD-reconfigurable, all-photonic interconnect for distributed and parallel systems (ndimensional-RAPID) where n can be 1, 2, or 3. nD-RAPID exploits optical architecture and technology design space that simultaneously tackles both fault-tolerance and dynamic bandwidth reallocation (DBR) of system architecture. Fault-tolerance in nD-RAPID is enabled through a multidimensional architecture. DBR is implemented by the row-column switching matrix using silicon-on-insulator (SOI)-based microring resonators that adapts to changes in communication patterns at runtime. Simulation results indicate that nD-RAPID outperformed other electrical networks for most traffic patterns. Results on DBR show that the proposed row-column switch organization significantly improves throughput and latency with a slight increase in electrical power consumption (∼0.4% for the worst case traffic).

AB - The increasing demand for higher communication bandwidth, reduced power consumption, and increased reliability combined with fundamental electrical signalling limitations is leading the drive for optics as an interconnect technology of choice for high-performance computing (HPC) systems. However, failure in any optical link can completely disrupt communication by isolating processing nodes in HPC systems. Moreover, while static allocation of wavelengths (channels) provides every node with equal opportunity for communication, it can also lead to network congestion for nonuniform traffic patterns. In this paper, we propose a multidimensional optoelectronic architecture, called nD-reconfigurable, all-photonic interconnect for distributed and parallel systems (ndimensional-RAPID) where n can be 1, 2, or 3. nD-RAPID exploits optical architecture and technology design space that simultaneously tackles both fault-tolerance and dynamic bandwidth reallocation (DBR) of system architecture. Fault-tolerance in nD-RAPID is enabled through a multidimensional architecture. DBR is implemented by the row-column switching matrix using silicon-on-insulator (SOI)-based microring resonators that adapts to changes in communication patterns at runtime. Simulation results indicate that nD-RAPID outperformed other electrical networks for most traffic patterns. Results on DBR show that the proposed row-column switch organization significantly improves throughput and latency with a slight increase in electrical power consumption (∼0.4% for the worst case traffic).

KW - Fault tolerance

KW - Optical interconnections

KW - Parallel processing

KW - Reconfigurable architectures

UR - http://www.scopus.com/inward/record.url?scp=70349417890&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70349417890&partnerID=8YFLogxK

U2 - 10.1109/JLT.2009.2026187

DO - 10.1109/JLT.2009.2026187

M3 - Article

AN - SCOPUS:70349417890

VL - 27

SP - 4634

EP - 4641

JO - Journal of Lightwave Technology

JF - Journal of Lightwave Technology

SN - 0733-8724

IS - 21

ER -